Computer Architecture Lab/SS2013/GROUP4 ASSIGNMENT2

Group 4 Ioannis Kotleas s122576 Chatzigeorgakidis Georgios s121078 Dean Roy Humphreys s120971 Tobias Bennike Aagren s112345

Instruction set for JOP inspired Stack Machine

Architecture specifications
The computer architecture that the following instruction set is intended for is a stack machine with three pipeline stages inspired by JOP. It consists of:
 * RAM virtually split into
 * ◦ Dual port cache for the Parameter stack
 * ◦ Cache for program memory

Pipeline stages:
 * Subroutine stack memory with depth of 100 for 100 nesting levels (to be adjusted as design requires)
 * Two registers (A & B) for the TOP and TOP-1 of the stack which are the arguements to the ALU
 * One register (p) holding the address pointing to TOS-2 in the Parameter stack
 * One register (VP) holding the address pointing to the variable section of the memory
 * One register (i) holding the address to the top of the Subroutine stack
 * The program counter register (PC)
 * The ALU
 * FETCH
 * DECODE
 * EXECUTE-LOAD-STORE

Instruction set specifications
The instructions are of fixed size. An immediate value is passed through an instruction field to the execution. Most of the instructions are handled within one clock cycle, as a result of the pipelining. Some instructions though require a second clock cycle in order to pass a parameter (value or address) through the program memory.

Instruction format:
 * Single cycle
 * Two cycle with parameter passing