Computer Architecture Lab/SS2013/Group3/Assignment1

AVR
Although the AVR architecture comes in 3 main families of microcontrollers, plus other more specialized series, we will be discussing the AVR32 architecture. This architecture is a reduced instruction set computer (RISC) with a 32-bit datapath

Architecture

 * data path on 32 bits
 * 3 to 7 stage pipeline
 * 15 general purpose registers
 * Big endianness
 * non-volatile flash memory for the program memory (has the advantage that the microcontroller keeps its program even after a power outage)
 * data memory consists of the register file, the I/O registers (for controlling the different peripherals on the microcontroller) and a SRAM memory
 * almost all AVR microcontroller have an internal EEPROM, which is for semi-permanent data storage
 * execution stage works in register-to-register mode

ARM
Based on the high market share of the ARM-based chips, we can safely say that it is the most used reduced instruction set computer (RISC) today.

Architecture

 * data path on 32 or 64 bits
 * 3 stage pipeline (up to ARM7 version), up to 13 stages for higher performance versions
 * 16 general purpose registers, some having special function (e.g. Stack Pointer, Link Register, Program Counter)
 * Bi-endianness, with little endian as default
 * support for 16 coprocessors, connected in a non-intrusive way
 * floating point based on VPF (Vector Floating Point) technology, as coprocessor
 * execution stage works in register-to-register mode

Instruction Set

 * ARM relies on a load/store architecture
 * 32-bit wide instructions
 * mostly single clock cycle execution
 * link register for fast leaf function calls
 * 2 priority level interrupt subsystem
 * supports add, subtract and multiply instructions, with some cores implementing integer divide
 * fold shifts/rotates into the data processing, reducing memory accesses and therefore improving pipeline efficiency

ARM resources

MIPS
MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Technologies (formerly MIPS Computer Systems, Inc.). Early versions had a 32-bit wide datapath, with latter ones at 64-bit.

Architecture (considering R2000 version)



 * data path on 32 bits
 * 5 pipeline stages:
 * Instruction Fetch
 * Instruction Decode
 * Execute
 * Memory read/store
 * Writeback


 * 32 32-bit general purpose registers (GPR)
 * could be booted either as big-endian or little-endian
 * support for up to 4 co-processors
 * could plug in the R2010 Floating Point Unit (FPU), having 32 32-bit registers (which could be used as 16 64-bit registers, for double precision)
 * external SRAM cache
 * internal DRAM (very slow writing time)
 * execution stage is of type register-to-register, the ALU obtaining values from the register file and writing back to the register file during writeback stage

Instruction Set
We are assuming an 32-bit MIPS processor, therefore the instruction size is of 32 bits. The instruction set is based around 3 types of instructions:
 * R - for operations based around values in the registers (arithmetic, logical, data transfer, unconditional jump register)
 * I - for operations based around values in the registers as well as an immediate value
 * J - for jump instructions, having only an immediate value specified (due to the need of all 26 bits for the address space)

Instruction formats are as follows:

For the complete list of instructions check this link.