Computer Architecture Lab/SS2014/group 4 lab 2

Proposals for ISAs

Proposal 1
A MIPS processor extended such that r1,r2 behave as windows into the top 2 elements of a return stack and r3,r4 behave as windows into a data stack. This should eliminate the performance decrease from function calls. The instruction set does not need to, but could, be changed from the standard MIPS32 ISA as common stack operations can already interpreted from the current instruction set.

For example ( using forth notation stack( before -- after ) )
 * dup ( a -- a a ): add $4 $4 $0
 * drop ( a -- ): add $0 $4 $0
 * swap ( a b -- b a ): add $4 $3 $0
 * over ( a b -- a b a ): add $5 $3 $0; add $4 $5 $0

Proposal 2
A stack machine with a data stack, return stack, variable stack, floating point stack and 28 temporary registers. Functional units are wired to the data stack.

Most instructions are 5-bit wide and are packed inside 32-bit words. Instructions that load an immediate value or jump are a full word wide and use 27 bits for the value. Instructions that can operate on a different stack than the data stack are 5-bit wide and use the following 5-bit to determine the point of operation.