Computer Architecture Lab/WS2007/Project -1 Lab2

MIssonPoSsible architecture:

Overview
We are using parts of the MIPS instruction set and architecture to archive a some what conmpatibility. In sum the processor possesses 25 instructions.

Registers
The architecture uses 32x32 bit registers, of which 29 are general purpose registers status register, zero register and a special register. (+ 32 bit program counter.)

Status Register Flags
The following table contains all status flags used for arithmetical operations and branch decisions:

The Overflow bit is set after multiplication operations arithmetic operations (MUL, MULU, ADD, SUB, shift operations) if the results needs more than 32bit. For additions it works as carry bit. The Zero bit is set if the result of the last operation was zero. The Negative flag is set, when the last operation was a signed-numbers operations and the result was negative. The random bit is randomly set after each clock cylce.

Instruction Set
The following are the six formats used for the core instruction set:

Simplified:

Supported operations:

ADD -- Add

ADDU -- Add unsigned

AND -- Bitwise and

BR -- Unconditional Branch

BZS -- Branch on zero set

BZC -- Branch on zero clear

BOS -- Branch on overflow set

BNS -- Branch on negative set

BNC -- Branch on negative clear

BOR -- Branch on random

JR -- Jump register

LLI -- Load lower immediate

LW -- Load word

NOOP -- no operation

OR -- Bitwise or

SLL -- Shift left logical 

SLLV -- Shift left logical variable

SRA -- Shift right arithmetic

SRL -- Shift right logical

SRLV -- Shift right logical variable

SUB -- Subtract

SUBU -- Subtract unsigned

SW -- Store word

XOR -- Bitwise exclusive or

OpCodes
The opcodes have a hamming distance of 2.

Address Modes

 * register (register-absolute addressing for direct jumps)
 * immediate (immediate-relative addressing for branches)

Sample Files
Samples Instruction Set 2