Computer Architecture Lab/WS2007/ZoWeAySi/ISA analysis

Einführung
Die MIPS (Microprocessor without interlocked pipline stages) Prozessoren bestehen aus einer RISC-Architektur. Diese wurden erstmals 1981 an der Stanford University entwickelt. Es wurden bis dato mehrere unterschiedliche MIPS-Prozessoren entwickelt. Die nachfolgende Beschreibung versucht mehr oder weniger die grundsätzlichen Instruktionstypen einer MIPS-Architektur zu erklären. Nach einer kurzen Einführung in Speicher, Register folgt die ISA eines MIPS.

Speicher
Da die verschiedenen MIPS-Prozessoren meist unterschiedliche Eigenschaften besitzen, wird hier der in den 80igern erfolgreiche R3000 kurz beschrieben. Dieser kann als Nachfolger vom R2000 betrachtet werden, der einen Daten und Instruktionscache von 32KB besaß, diese Speichergrösse wurde beim R3000 auf jeweils 64KB erhöht. Im Gegensatz zu vielen seinen Nachfolgern besitzt der R3000 keinen L2-Cache. Grundsätzlich kann man sagen das die MIPS-Prozessoren im Besitz eines Daten-und Instruktionscache sind, zusätzlich existiert bei den meisten Prozessoren ein L2-Cache, dessen Grösse oft unterschiedlich ist.

Register
Es existieren 32 Register.

ISA
Die Gesamtlänge einer MIPS Instruktion beträgt 32 bit. Dabei gibt es drei verschiedene Arten von Instruktionen, man unterscheidet zwischen R-type (register), I-type (immediate type) und J-type (jump type). Bevor diese Typen genauer erklärt werden hier noch eine Liste mit den in MIPS-Architekturen zur Verfügung stehenden Operationen:


 * arithmetische Operationen: add, sub,.. (R-und I-type)
 * Datentransfer: lw (laden), sw (speichern),.. (R-und I-type)
 * logische Operationen: and, or,.. (R-und I-type)
 * bitweise shift: sll (shift left logical), srl (shift right logical),.. (R-type)
 * bedingte Abzweigung: beq (branch on equal,.. (I-type)
 * einfacher Sprung: j (jump), jr (jump register),.. (R- und J-type)

Nun die Erklärung zu den unterschiedlichen Instruktionstypen.

R-, I- und J-type Instruktionen
MIPS Felder bei R-type


 * op: Operation die durchgeführt werden soll
 * rs: der erste Operand
 * rt: der zweite Operand
 * rd: Zielregister für die Operation op
 * shamt: Shiftbetrag, 0 falls nicht verwendet
 * funct: wählt die spezifische Variante der Operation op

MIPS Felder bei I-type


 * op: Operation die durchgeführt werden soll
 * rs: der erste Operand
 * rt: der zweite Operand
 * address: damit kann man einen größeren Bereich von 32,768 Bytes ansprechen.

MIPS Felder bei J-type


 * op: Operation die durchgeführt werden soll, jump-Befehle
 * target: Zieladresse des Sprungbefehls

Auffällig ist das bei den ersten beiden Instruktionsformaten die ersten 3 Felder gleich sind. Beim I-type sind die letzten 3 Felder zu einem address-Feld zusammengefasst. Welches der drei Formate bei der Ausführung durch die Hardware gewählt wird hängt vom Wert des ersten Feldes (op, Operation) ab. Die Hardware weiss je nach op-Feld ob es sich um ein R-, I- oder J-type handelt. Welche Operationen mit welchen Formaten verwendet werden, wird anschließend genauer erläutert.

Operationen im R-,I- und J-Format
Nachfolgend werden für jeden Befehlsformat Operationen vorgestellt. Die Addition, Subtraktion verwenden den R-type.

Wie man sieht verwenden die Addition und Subtraktion den selben Operationscode 0, die Unterscheidung für die Hardware wird in diesem Fall aus op-Code und funct-Code erreicht. Durch berücksichtigen des funct-Codes (bei add 32, bei sub 34) kann die Hardware genau festlegen welche Operation angewendet werden soll. Befehle die den I-type verwenden sind das Laden und Speichern von Worten.

Beim J-type wird ein Sprung auf eine Zieladresse ermöglicht. Mehr Funktionalität hat dieses Instruktionsformat nicht.

Anwendungen
MIPS-Prozessoren finden Verwendung in Navigations systemen, Satellitenreceivern, Sony-und Nintendospielkonsolen, Dreambox. etc.

Referenzen

 * Computer Organization & Design 2nd Edition, David A. Patterson and John L. Hennessy
 * http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Mips/format.html
 * http://web.archive.org/web/20050208224500/http://www.csl.cornell.edu/courses/ece314/resources/MIPS_Vol1.pdf
 * http://en.wikipedia.org/wiki/MIPS_architecture

Overview
The Zilog Z80 is an 8 Bit CPU with a 16 bit wide address bus. It features a CISC instruction set which is binary compatible to the Intel 8080 microprocessor but extends it with some new instructions and registers.

Registers
The Z80 features two identical sets of general purpose registers which are swappable by special instructions. It has also a set of special purpose registers.

General purpose registers

 * A: 8 bit accumulator
 * F: 8 bit flag register
 * BC: two 8 bit or one 16 bit general purpose register
 * DE: two 8 bit or one 16 bit general purpose register
 * HL: 16 bit accumulator, used for memory addressing, also usable as two 8 bit registers

Special purpose registers

 * I: 8 bit interrupt register
 * R: 8 bit refresh register
 * IX: 16 bit index register for memory addressing
 * IY: 16 bit index register for memory addressing
 * SP: 16 bit stack pointer
 * PC: 16 bit program counter

Featured flags

 * S: sign
 * Z: zero
 * H: halfcarry, used for BCD adjustment
 * P/V: parity/overflow, parity at logical operations, overflow at arithmetical operations
 * N: add/subtract flag, used for BCD adjustment
 * C: carry

Instruction formats
A Z80 instruction may consist of a prefix byte, an 8 bit opcode, a displacement byte and 0-2 bytes of immediate data. Valid instruction are therefore byte sequences of the form or
 * [prefix byte,] opcode [,displacement byte] [,immediate data]
 * two prefix bytes, displacement byte, opcode

Prefix byte
4 opcodes out of the 10 unused opcodes from the Intel 8080 are used as prefix bytes. Prefix bytes alters the meaning of the following opcode. They may switch, for example, the usage of the HL register to the usage of de IX or IY index register.

As mentioned above, there is also an instruction format possible which utilizes two prefix bytes.

Opcode
The opcode describes the applicable operation and encodes also the register operands. The bit encoding is non-orthogonal and additionally depends on the prefix bytes. Prefix and opcode also determine if there is a displacement byte and how many bytes of immediate data have to be read.

Displacement byte
Depending on prefix and opcode a displacement byte may follow. The displacement byte is interpreted as number within the range -128..+127 and is usually used as displacement for memory addressing or for relative jumps.

Immediate data
Depending on prefix and opcode 0-2 bytes of immediate data may follow. They are usually used to encode memory addresses or constants.

Instructions
The Z80 features the following groups of instructions


 * Load instructions for 8 bit and 16 bit
 * block transfer and search
 * 8 bit arithmetical- and logical-operations
 * 16 bit arithmetic on the HL register and the index registers
 * 8 bit rotation and shift
 * bit manipulation (set, reset and test)
 * jump, call and return
 * port I/O

Addressing modes
As instruction operands generally register operands, immediate operands or memory operands are possible. The available addressing modes depend highly on the instruction itself.

The opcodes are only 8 bits wide and are therefore not capable to address many registers. Because of this only the 8 bit load operation which copies the source registers contents into the destination register allows free selection of the two register operands. All other instructions which use more than one register operand are restricted to the use of the accumulator register as an implicit second operand.

Addressing mode details:


 * Immediate: operand is encoded as 8 bit immediate data
 * Immediate extended: operand is encoded as 16 bit immediate data
 * Modified Page Zero Addressing: call instruction to any of 8 locations in page zero
 * Relative Addressing: PC-relative jumps in the range -128..+127
 * Extended Addressing: memory address is encoded as 16 bit immediate data (for jumps or memory operands)
 * Indexed Addressing: memory addressing with index register + displacement
 * Register Addressing: operand in register
 * Implied Addressing: instruction expects operand in specific register (e.g. accumulator)
 * Register Indirect Addressing: memory addressing with 16 bit register (BC, DE or HL)
 * Bit Addressing: set, reset or test single bits in the accumulator

Usage

 * arcade games
 * home computers (in combination with the CP/M operating system)
 * scientific calculators
 * game consoles
 * embedded systems

Overview
The ATmega16 core is a RISC design and uses a harvard architecture. It furthermore features a single level pipeline for instruction prefetching.

Memory
The ATmega16 has no cache. It is equipped with 8Kx16 of ISP Flash memory, 512 bytes of EEPROM and 1K of SRAM.

Registers
It features an 8-bit wide databus, 32 general purpose registers and various special registers. Six of these 8 bit wide registers can be combined to three 16 bit (X, Y and Z) wide registers for indirect addressing, while one of these registers can be used as an address pointer for look up tables in flash. Some of these special registers are:
 * Status Register
 * Stack Pointer Register
 * Program Counter Register
 * EEPROM Data, Control and Address Register
 * various Timer and ADC registers

I/O
The ATmega16 further provides various typical microcontroller features like GPI/O lines, timers, ADCs, a SPI interface and many more, but these features, however interesting they might seem are out of the scope of this document.

ISA
The ATmega16 instruction set consists of 131 instructions. For almost all arithmetic instructions it guarantees single clock execution. The most notable exceptions are multiplication, subroutine calls and data transfer instructions.

Addressing modes

 * Register direct addressing
 * I/O direct addressing
 * Direct program addressing
 * Data indirect addressing (X, Y and Z registers)
 * Data indirect with post increment (- " -)
 * Data indirect with pre decrement (- " -)
 * Data indirect with displacement (- " -)

Instruction format
Most instructions consist of a 16 bit format, some are 32 bits long. Most instructions are identified by bits 0-5 , but sometimes additional bits are used (usually bit 13-15).

Instructions
The instruction set breaks down to 5 classes. For each of these classes a typical example is specified.

Arithmetic and logic instructions
ADD Rd, Rr - Adds two registers.

Branch instructions
CALL k - Direct subroutine call

Data transfer instructions
STD Y+q, Rr - Store indirect with displacement

Bit and bit-test instructions
SBI P, b - Set bit in I/O Register.

MCU controll instructions
WDR - Resets the watchdog.

Usage
The ATmega16 is widely used as a general purpose microcontroller ranging from applications in the automotive industry to applications in hobbyist embedded systems.

Cell - SPU
The Cell Synergestic Processor Unit is a mixture of a general-purpose processor, with an optimized ISA and special hardware for games, media and broadband systems. The SPU supports 16 bit and 32 bit signed integers and limited support for 8 bit unsigned integers, both represented in two's complement. Further on it supports single-precision and double-precision floating-point data.

Features

 * 128 general-purpose registers (GPR) with 128 bits.
 * 128-bit SIMD.
 * load/store architecture.
 * ISA support to eliminate branches.
 * optimized for single-precision floating-point support.
 * channel architecture.
 * big endian byte ordering.

Memory
The SPU has no real cache and no direct access to VRAM. It contains a private memory, called local storage, which is externally accessible. The address space of the local storage is 232 bytes, though an implementation generally has a smaller actual memory size.

Instruction Formats

 * Six basic formats, each 32 bits long.
 * Ra, Rb, Rc specify a GPR used as source or target.
 * Rt specifies a GPR used as target.
 * Ix specifies a x bit immediate.


 * {|border="2" cellpadding="0" cellspacing="0" style="margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse; font-size: 95%;"


 * -align="center"
 * style="width:88px;background:#E6E6FA" |Op11
 * style="width:56px" |Rb7
 * style="width:56px" |Ra7
 * style="width:56px" |Rt7
 * }


 * {|border="2" cellpadding="0" cellspacing="0" style="margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse; font-size: 95%;"


 * -align="center"
 * style="width:32px;background:#E6E6FA" |Op4
 * style="width:56px" |Rt7
 * style="width:56px" |Rb7
 * style="width:56px" |Ra7
 * style="width:56px" |Rc7
 * }


 * {|border="2" cellpadding="0" cellspacing="0" style="margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse; font-size: 95%;"


 * -align="center"
 * style="width:88px;background:#E6E6FA" |Op11
 * style="width:56px;background:#F5DEB3" |I77
 * style="width:56px" |Ra7
 * style="width:56px" |Rt7
 * }


 * {|border="2" cellpadding="0" cellspacing="0" style="margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse; font-size: 95%;"


 * -align="center"
 * style="width:72px;background:#E6E6FA" |Op9
 * style="width:128px;background:#F5DEB3" |I1616
 * style="width:56px" |Rt7
 * }


 * {|border="2" cellpadding="0" cellspacing="0" style="margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px #aaa solid; border-collapse: collapse; font-size: 95%;"


 * -align="center"
 * style="width:56px;background:#E6E6FA" |Op7
 * style="width:144px;background:#F5DEB3" |I1818
 * style="width:56px" |Rt7
 * }

Instructions

 * Memory-Load/Store Instructions


 * Constant-Formation Instructions


 * Integer and Logical Instructions


 * Shift and Rotate Instructions


 * Compare, Branch and Halt Instructions


 * Hint-For-Branch Instructions


 * Floating-Point Instructions


 * Control Instructions


 * Channel Instructions

Referenzen
SPU Assembly Language Specification

SPU ISA Specification

SIMD Math Library Specification