Computer Architecture Lab/WS2007/ZoWeAySi/Instruction Set II

Features

 * 32-bit RISC processor
 * Load/Store architecture
 * Harvard architecture
 * 32 32-bit general purpose registers
 * 32-bit instruction width
 * 4 pipeline stages
 * memory mapped IO

GP Registers
Our Processor has 32 GP registers:


 * $0	always zero
 * $1..30 arbitrary
 * $31 Stack Pointer

Flags
Our Processor features 4 flags in the flag register:


 * CF .. Carry Flag
 * SF .. Sign Flag
 * ZF .. Zero Flag
 * OF .. Overflow Flag

Instruction Formats
R-Type:

I-Type: