Computer Architecture Lab/Winter2006/KammPuffBili/InstructionSet

General

 * 16 16-bit registers
 * flags: Z, C, V, N
 * Z: all bits of the last result are zero
 * C: 17^th bit of the last result
 * N: 16^th bit of the last result
 * V: overflow, after sub/cmp it is $$r1:15 \oplus r2:15 \oplus N \oplus C$$, the latter two according to the result
 * I: allow interrupts
 * P: parity of the last result


 * any register as return address
 * Some parts come from the Alpha architecture. "ldpgm" had to be there, because those were painfully missing from the SPEAR Architecture. The handling of branches is inspired by the Intel x86.
 * separate registers for interrupt vectors - read and written through "ldvec" / "stvec"

The processor uses a Harvard architecture; although it has not prevailed in mainstream-architectures, it is still used in embedded processors such as the Atmel AVR. The separation of code- and data-memory is not flexible enough for mainstream systems, but with small embedded processors the program code tends to be fixed anyway. A Harvard architecture enables the processor to make use of more memory (which is an issue when the adress space is limited to 64k), and the program code can be read from a ROM directly. A transient failure thus cannot destroy the program by overwriting its code section.

Instruction Set
Instruction Set of marca processor

Pipelining
We are considering a 4-stage pipeline:
 * instruction fetch
 * instruction decode
 * execution/memory access
 * write back

This scheme is similar to the one used in the MIPS architecture, only execution and write back stage are drwan together. For our architecture does not support indexed adressing, it does not need the ALU's result and can work in parallel, having the advantage of reducing the possible hazards.