Computer Architecture Lab/Winter2006/PolzerJahn/Bin2iniram

Bin2IniRAM
Bin2IniRAM is a simple VHDL code generator for SISP written in Python. It generates a VHDL entity, representing an initialised RAM, from a binary file.

Usage
Synopsis: bin2iniram.py -a address width][-d data width][-o outfile][-m memory interface type binary_inputfile

The following parameters control the execution of the program:


 * -a, --address_width: Controls the address width of the generated memory interface (default: 16).


 * -d, --data_width: Controls the data width of the generated memory interface (default: 12).


 * -o, --outfile: The name of the file where the generated VHDL code should be written (default: prog_mem.vhd).


 * -m, --memory_interface: The type of the memory interface. Can be either "single" (default) or "dual".

Download
You can download the current version of Bin2IniRAM as archive here.

Version History
0.4: 13-01-2007 0.3: 10-01-2007 0.2: 20-12-2006 0.1: 19-12-2006
 * script looks for templates in its execution path instead of cwd
 * added support for dual port memory interfaces (flag -m dual)
 * fixed bugs, created vhdl code is now syntactically correct
 * initial version