Computer Architecture Lab/Winter2006/PolzerJahn/Design

Basic data

 * 16bit RISC CPU
 * 16 internal registers
 * von Neumann architecture
 * 16bit address bus
 * 32bit external data bus
 * two instruction widths (16 bit, 32bit)
 * External memory: 128 kB
 * Connection to a PC: standard serial interface (RS-232)
 * Number format: little endian
 * Signed arithmetic (two's complement)

Instruction set
Note: Instructions which take up 32 bit have an opcode higher than or equal to 0x20.
 * Basic operations:
 * Logical operations:
 * Arithmetic operations:
 * Shift operations:
 * Compare operations:
 * Input/output operations:
 * Jump operations:

Instruction format
8-bit Opcode, two 4-bit register numbers 8-bit Opcode, 4-bit register number (optional), 16 bit immediate value
 * Standard Instruction
 * Extended instruction

Pipeline
SIPS uses a four stage pipeline:
 * fetch
 * decode
 * execute
 * write back

This file contains a detailed graphical description of each stage.