Computer Architecture Lab/Winter2006/SHWH/Detailed description

Version 0.05

This version is also available as [[media:DescriptionTanteEmma.pdf|PDF]].

Features

 * 16-bit RISC processor
 * Harvard architecture
 * 40 instructions
 * 3 pipeline stages
 * 16 16-bit GPRs
 * 16-bit internal and external bus
 * Fix instruction width
 * Little Endian number format

Instruction Format
or

or

Pipeline
Our processor "Tante Emma" has 3 pipeline stages:
 * Instruction fetch
 * Instruction decode
 * Execute