Computer Architecture Lab/Winter2007/SHWH/Detailed description

Version 0.05

This version is also available as [[media:DescriptionTanteEmma.pdf|PDF]].

Features

 * Single core 16-bit RISC processor
 * Harvard architecture
 * 36 instructions
 * 4 pipeline stages
 * 14 16-bit GPRs
 * reg0 --> zero register
 * reg15 --> return address register
 * 16-bit internal and 16-bit external bus
 * 4 bit(for branch and LDIs) and 8 bit(for others) opcode width
 * Little Endian number format

Pipeline
Our processor "Tante Emma" has 4 pipeline stages:
 * Instruction fetch - Load command to the command buffer; increment PC
 * Instruction decode - Initialize operands from registers; generate processor internal control signals
 * Execute - ALU makes operation, calculation of a address in load/store commands
 * Writeback - load/store, write result in register

Pin Numbers
For the OUT and IN operation we have to define a pinnumber. Use these pin numbers for the following pysical device.

UART RX TX
In this section we want to describe how to handle the UART within an assembler program.

UART Receive
When we want to receive a byte from UART, we do a in operation. Then the processor is stalled until the byte is received.

UART Transmit
When we are writing a byte to the UART TX register the prozessor will be halted until the byte was sent.