Digital Electronics

Back to: Topic:Electronic Engineering Welcome to the course EE 111.
 * Digital Electronics in Electrical/Electronics Engineering

Lecture plan

 * EE 111 Digital Electronics
 * Lecture 1, Introduction to Binary, Octal and Hexadecimal Mathematics
 * Lecture 2, Digital Logic
 * Analysis of the inside of the basic logic types TTL MOS CMOS
 * Lecture 3, Combinatorial Functions
 * Basic logic gates
 * Lecture 4, Karnaugh Map Reductions
 * Lecture 5, Arithmetic
 * Half Adder, Full Adder
 * Lecture 6, Flip-flops
 * JK SR D T flipflops/latches
 * Mid-term Exam
 * Lecture 7, Sequential Logic
 * Lecture 8, Memory Elements
 * Lecture 9, Registers and Counters
 * Lecture 10, Advanced Sequential Circuits
 * Lecture 11, Logic Simulation
 * Lecture 12, High Level Language Logic Modelling and Synthesis
 * Final Exam
 * Lecture 11, Logic Simulation
 * Lecture 12, High Level Language Logic Modelling and Synthesis
 * Final Exam
 * Lecture 12, High Level Language Logic Modelling and Synthesis
 * Final Exam

Datasheets Relevant
74=Lower Voltage 40=Higher Voltage

Reference books
Digital Principles And Design - Donald D Givone Sanador 11:38, 13 March 2009 (UTC)Santosh A G

Research projects
Debugging for RedHawk Duels: When trying to compile ship_proto.v first open ship_proto_assignment_defaults.qdf. Then change INCREMENTAL_COMPILATION to off (line 595). The code should then compile.

If this does not work, you may have to add the statement >>set_global_assignment -name INCREMENTAL_COMPILATION OFF<< in the .qdf file

Active participants

 * Kaushani123 18:50, 5 April 2009 (UTC)