Materials Science and Engineering/Diagrams/Optimization of Devices

Responsivity
The ratio of generated photocurrent to incident light power, typically expressed in A/W when used in photoconductive mode. The responsivity may also be expressed as a quantum efficiency, or the ratio of the number of photogenerated carriers to incident photons and thus a unitless quantity.

Dark Current
The current through the photodiode in the absence of light, when it is operated in photoconductive mode. The dark current includes photocurrent generated by background radiation and the saturation current of the semiconductor junction. Dark current must be accounted for by calibration if a photodiode is used to make an accurate optical power measurement, and it is also a source of noise when a photodiode is used in an optical communication system.

Noise-Equivalent Power
(NEP) The minimum input optical power to generate photocurrent, equal to the rms noise current in a 1 hertz bandwidth. The related characteristic detectivity (D) is the inverse of NEP, 1/NEP; and the specific detectivity ($$D^\star$$) is the detectivity normalized to the area (A) of the photodetector, $$D^\star=D\sqrt{A}$$. The NEP is roughly the minimum detectable input power of a photodiode.

Comparison with Photomultipliers
Advantages compared to photomultipliers:


 * 1) Excellent linearity of output current as a function of incident light
 * 2) Spectral response from 190 nm to 1100 nm (silicon), longer wavelengths with other semiconductor materials
 * 3) Low noise
 * 4) Ruggedized to mechanical stress
 * 5) Low cost
 * 6) Compact and light weight
 * 7) Long lifetime
 * 8) High quantum efficiency, typically 80%
 * 9) No high voltage required

Disadvantages compared to photomultipliers:


 * 1) Small area
 * 2) No internal gain (except avalanche photodiodes, but their gain is typically 10²–10³ compared to up to 108 for the photomultiplier)
 * 3) Much lower overall sensitivity
 * 4) Photon counting only possible with specially designed, usually cooled photodiodes, with special electronic circuits
 * 5) Response time for many designs is slower

PN or PIN Diode

 * 1) Due to the intrinsic layer, a PIN photodiode must be reverse biased (Vr). The Vr increases the depletion region allowing a larger volume for electron-hole pair production, and reduces the capacitance thereby increasing the bandwidth.
 * 2) The Vr also introduces noise current, which reduces the S/N ratio. Therefore, a reverse bias is recommended for higher bandwidth applications and/or applications where a wide dynamic range is required.
 * 3) A PN photodiode is more suitable for lower light applications because it allows for unbiased operation.

Photodiode Array
Hundreds or thousands (up to 2048) photodiodes of typical sensitive area 0.025mmx1mm each arranged as a one-dimensional array, which can be used as a position sensor. One advantage of photodiode arrays (PDAs) is that they allow for high speed parallel read out since the driving electronics may not be built in like a traditional CMOS or CCD sensor.

Efficiency Terms
The proportion of electrons able to cross the base and reach the collector is a measure of the BJT efficiency. The heavy doping of the emitter region and light doping of the base region cause many more electrons to be injected from the emitter into the base than holes to be injected from the base into the emitter. The common-emitter current gain is represented by βF or hfe. It is approximately the ratio of the DC collector current to the DC base current in forward-active region, and is typically greater than 100. Another important parameter is the common-base current gain, αF. The common-base current gain is approximately the gain of current from emitter to collector in the forward-active region. This ratio usually has a value close to unity; between 0.98 and 0.998. Alpha and beta are more precisely related by the following identities (NPN transistor):

$$\alpha_T = \frac{I_\mathrm{C}}{I_\mathrm{E}}$$

$$\beta_F = \frac{I_\mathrm{C}}{I_\mathrm{B}}$$

$$\beta_F = \frac{\alpha_T}{1 - \alpha_T}\iff \alpha_T = \frac{\beta_F}{\beta_F+1}$$

Germanium
The germanium transistor was more common in the 1950s and 1960s, and while it exhibits a lower "cut off" voltage, making it more suitable for some applications, it also has a greater tendency to exhibit thermal runaway.

Heterojunction BJT
The heterojunction bipolar transistor (HBT) is an improvement of the BJT that can handle signals of very high frequencies up to several hundred GHz. It is common nowadays in ultrafast circuits, mostly RF systems.[5][6] Heterojunction transistors have different semiconductors for the elements of the transistor. Usually the emitter is composed of a larger bandgap material than the base. The figure shows that this difference in bandgap allows the barrier for holes to inject backward into the base, denoted in figure as Δφp, to be made large, while the barrier for electrons to inject into the base Δφn is made low. This barrier arrangement helps reduce minority carrier injection from the base when the emitter-base junction is under forward bias, and thus reduces base current and increases emitter injection efficiency.

The improved injection of carriers into the base allows the base to have a higher doping level, resulting in lower resistance to access the base electrode. In the more traditional BJT, also referred to as homojunction BJT, the efficiency of carrier injection from the emitter to the base is primarily determined by the doping ratio between the emitter and base, which means the base must be lightly doped to obtain high injection efficiency, making its resistance relatively high. In addition, higher doping in the base can improve figures of merit like the Early voltage by lessening base narrowing.

The grading of composition in the base, for example, by progressively increasing the amount of germanium in a SiGe transistor, causes a gradient in bandgap in the neutral base, denoted in the figure by ΔφG, providing a "built-in" field that assists electron transport across the base. That drift component of transport aids the normal diffusive transport, increasing the frequency response of the transistor by shortening the transit time across the base.

Two commonly used HBTs are silicon–germanium and aluminum gallium arsenide, though a wide variety of semiconductors may be used for the HBT structure. HBT structures are usually grown by epitaxy techniques like MOCVD and MBE.

Gate

 * 1) The threshold voltage (and consequently the drain to source on-current) is modified by the work function difference between the gate material and channel material. Because polysilicon is a semiconductor, its work function can be modulated by adjusting the type and level of doping. Furthermore, because polysilicon has the same bandgap as the underlying silicon channel, it is quite straightforward to tune the work function, so as to achieve low threshold voltages for both NMOS and PMOS devices. By contrast the work functions of metals are not easily modulated, so tuning the work function to obtain low threshold voltages becomes a significant challenge. Additionally, obtaining low threshold devices on both PMOS and NMOS devices would likely require the use of different metals for each device type, introducing additional complexity to the fabrication process.
 * 2) In the MOSFET IC fabrication process, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better performing transistors. Such high temperature steps would melt some metals, limiting the types of metals that could be used in a metal-gate based process.

Junction Design
The drain induced barrier lowering of the threshold voltage and channel length modulation effects upon I-V curves are reduced by using shallow junction extensions. In addition, halo doping can be used, that is, the addition of very thin heavily doped regions of the same doping type as the body tight against the junction walls to limit the extent of depletion regions.

The capacitive effects are limited by using raised source and drain geometries that make most of the contact area border thick dielectric instead of silicon.

These various features of junction design are shown (with artistic license) in the figure.

Junction leakage is discussed further in the section increased junction leakage.

FinFETS
The FinFET, see figure to right, is a double gate device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering.

NMOS Logic
n-channel MOSFETs are smaller than p-channel MOSFETs and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of NMOS logic which uses n-channel MOSFETs exclusively. However, unlike CMOS logic, NMOS logic consumes power even when no switching is taking place. With advances in technology, CMOS logic displaced NMOS logic in the 1980s to become the preferred process for digital chips.

Higher Subthreshold Conduction
Because of small MOSFET geometries, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the "on" case and low current in the "off" case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips.

Increased Gate-Oxide Leakage
The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel, leading to increased power consumption.

Insulators (referred to as high-k dielectrics) that have a larger dielectric constant than silicon dioxide, such as group IVb metal silicates e.g. hafnium and zirconium silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards. Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance. (Capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness.) All else equal, a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in conduction band energy between the semiconductor and the dielectric (and the corresponding difference in valence band energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 eV. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant.

Increased Junction Leakage
To make devices smaller, junction design has become more complex, leading to higher doping levels, shallower junctions, "halo" doping and so forth, all to decrease drain-induced barrier lowering. See also section on junction design. To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must be curtailed, increasing junction leakage. Heavier doping also is associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage.

Lower Transconductance
The transconductance of the MOSFET decides its gain and is proportional to hole or electron mobility (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.

Interconnect Capacitance
Traditionally switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, interconnect capacitance (the capacitance of the wires connecting different parts of the chip) is becoming a large percentage of capacitance. Signals have to travel through the interconnect, which leads to increased delay and lower performance.

Heat Production
The ever-increasing density of MOSFETs on an integrated circuit is creating problems of substantial localized heat generation that can impair circuit operation. Circuits operate slower at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling methods are now required for many integrated circuits including microprocessors.

Process Variations
With MOSFETS becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness etc., and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See design for manufacturability, reliability engineering, six sigma and statistical process control.

First Generation Photovoltaics
The first generation photovoltaic cell consists of a large-area, single-crystal, single layer p-n junction diode, capable of generating usable electrical energy from light sources with the wavelengths of sunlight. These cells are typically made using a diffusion process with silicon wafers. First-generation photovoltaic cells (also known as silicon wafer-based solar cells) are the dominant technology in the commercial production of solar cells, accounting for more than 86% of the terrestrial solar cell market.

Second Generation Photovoltaics
The second generation of photovoltaic materials is based on the use of thin epitaxial deposits of semiconductors on lattice-matched wafers. There are two classes of epitaxial photovoltaics - space and terrestrial. Space cells typically have higher AM0 efficiencies (28-30%) in production, but have a higher cost per watt. Their "thin-film" cousins have been developed using lower-cost processes, but have lower AM0 efficiencies (7-9%) in production and are questionable for space applications. The advent of thin-film technology contributed to a prediction of greatly reduced costs for thin film solar cells that has yet to be achieved. There are currently (2007) a number of technologies/semiconductor materials under investigation or in mass production. Examples include amorphous silicon, polycrystalline silicon, micro-crystalline silicon, cadmium telluride, copper indium selenide/sulfide. An advantage of thin-film technology theoretically results in reduced mass so it allows fitting panels on light or flexible materials, even textiles. The advent of thin GaAs-based films for space applications (so-called "thin cells") with potential AM0 efficiencies of up to 37% are currently in the development stage for high specific power applications. Second generation solar cells now comprise a small segment of the terrestrial photovoltaic market, and approximately 90% of the space market.

Third Generation Photovoltaics
Third-generation photovoltaics are proposed to be very different from the previous semiconductor devices as they do not rely on a traditional p-n junction to separate photogenerated charge carriers. For space applications quantum well devices (quantum dots, quantum ropes, etc.) and devices incorporating carbon nanotubes are being studied - with a potential for up to 45% AM0 production efficiency. For terrestrial applications, these new devices include photoelectrochemical cells, polymer solar cells, nanocrystal solar cells, Dye-sensitized solar cells and are still in the research phase.

Fourth Generation Photovoltaics
A hypothetical 'fourth-generation' of solar cells may consist of composite photovoltaic technology, in which polymers with nano particles can be mixed together to make a single multispectrum layer. Then the thin multispectrum layers can be stacked to make multispectrum solar cells more efficient and cheaper based on polymer solar cell and multijunction technology used by NASA on Mars missions. The layer that converts different types of light is first, then another layer for the light that passes and last is an infra-red spectrum layer for the cell—thus converting some of the heat for an overall solar cell composite. Current research is being conducted under a DARPA grant to determine if this technology is viable. Companies working on fourth-generation photovoltaics include Xsunx, Konarka Technologies, Inc., Nanosolar, Dyesol and Nanosys. Research is also being done in this area by the USA's National Renewable Energy Laboratory.

Maximum Power Point
A solar cell may operate over a wide range of voltages (V) and currents (I). By increasing the resistive load on an irradiated cell continuously from zero (a short circuit) to a very high value (an open circuit) one can determine the maximum-power point, the point that maximizes V×I, that is, the load for which the cell can deliver maximum electrical power at that level of irradiation.

The maximum power point of a photovoltaic varies with incident illumination. For systems large enough to justify the extra expense, a maximum power point tracker tracks the instantaneous power by continually measuring the voltage and current (and hence, power transfer), and uses this information to dynamically adjust the load so the maximum power is always transferred, regardless of the variation in lighting.

Energy Conversion Factor
A solar cell's energy conversion efficiency (η, "eta"), is the percentage of power converted (from absorbed light to electrical energy) and collected, when a solar cell is connected to an electrical circuit. This term is calculated using the ratio of the maximum power point, Pm, divided by the input light irradiance (E, in W/m²) under standard test conditions (STC) and the surface area of the solar cell (Ac in m²).

$$\eta = \frac{P_{m}}{E \times A_c}$$

STC specifies a temperature of 25°C and an irradiance of 1000 W/m² with an air mass 1.5 (AM1.5) spectrum. These correspond to the irradiance and spectrum of sunlight incident on a clear day upon a sun-facing 37°-tilted surface with the sun at an angle of 41.81° above the horizon. This condition approximately represents solar noon near the spring and autumn equinoxes in the continental United States with surface of the cell aimed directly at the sun. Thus, under these conditions a solar cell of 12% efficiency with a 100 cm2 (0.01 m2) surface area can be expected to produce approximately 1.2 watts of power.

Fill Factor
Another defining term in the overall behavior of a solar cell is the fill factor (FF). This is the ratio of the maximum power point divided by the open circuit voltage (Voc) and the short circuit current (Isc):

$$FF = \frac{P_{m}}{V_{oc} \times I_{sc}} = \frac{\eta \times A_c \times E}{V_{oc} \times I_{sc}}$$

Quantum Efficiency
As described above, when a photon is absorbed by a solar cell it is converted to an electron-hole pair. This electron-hole pair may then travel to the surface of the solar cell and contribute to the current produced by the cell; such a carrier is said to be collected. Alternatively, the carrier may give up its energy and once again become bound to an atom within the solar cell without reaching the surface; this is called recombination, and carriers that recombine do not contribute to the production of electrical current.

Quantum efficiency refers to the percentage of photons that are converted to electric current (i.e., collected carriers). External quantum efficiency is the fraction of incident photons that are converted to electrical current, while internal quantum efficiency is the fraction of absorbed photons that are converted to electrical current. Mathematically, internal quantum efficiency is related to external quantum efficiency by the reflectance of the solar cell; given a perfect antireflection coating, they are the same.

Quantum efficiency should not be confused with energy conversion efficiency, as it does not convey information about the power collected from the solar cell. Furthermore, quantum efficiency is most usefully expressed as a spectral measurement (that is, as a function of photon wavelength or energy). Since some wavelengths are absorbed more effectively than others in most semiconductors, spectral measurements of quantum efficiency can yield information about which parts of a particular solar cell design are most in need of improvement.

Thin Films
The various thin-film technologies currently being developed reduce the amount (or mass) of light absorbing material required in creating a solar cell. This can lead to reduced processing costs from that of bulk materials (in the case of silicon thin films) but also tends to reduce energy conversion efficiency, although many multi-layer thin films have efficiencies above those of bulk silicon wafers.

CdTe
Cadmium telluride is an efficient light-absorbing material for thin-film solar cells. Compared to other thin-film materials, CdTe is easier to deposit and more suitable for large-scale production. Despite much discussion of the toxicity of CdTe-based solar cells, this is the only technology (apart from amorphous silicon) that can be delivered on a large scale, as shown by First Solar and Antec Solar. There is a 40 megawatt plant in Ohio (USA) and a 10 megawatt plant in Germany. First Solar is scaling up to a 100 MW plant in Germany and started building another 100 MW plant in Malaysia (2007).

The perception of the toxicity of CdTe is based on the toxicity of elemental cadmium, a heavy metal that is a cumulative poison. Scientific work, particularly by researchers of the National Renewable Energy Laboratories (NREL) in the USA, has shown that the release of cadmium to the atmosphere is lower with CdTe-based solar cells than with silicon photovoltaics and other thin-film solar cell technologies.

Copper-Indium Selenide
The materials based on CuInSe2 that are of interest for photovoltaic applications include several elements from groups I, III and VI in the periodic table. These semiconductors are especially attractive for thin film solar cell application because of their high optical absorption coefficients and versatile optical and electrical characteristics which can in principle be manipulated and tuned for a specific need in a given device. CIS is an abbreviation for general chalcopyrite films of copper indium selenide (CuInSe2).

When gallium is substituted for some of the indium in CIS, the material is sometimes called CIGS, or copper indium/gallium diselenide, a solid mixture of the semiconductors CuInSe2 and CuGaSe2, often abbreviated by the chemical formula CuInxGa(1-x)Se2. Unlike the conventional silicon based solar cell, which can be modelled as a simple p-n junction (see under semiconductor), these cells are best described by a more complex heterojunction model. The best efficiency of a thin-film solar cell as of December 2005 was 19.5% with CIGS absorber layer. Higher efficiencies (around 30%) can be obtained by using optics to concentrate the incident light. The use of gallium increases the optical bandgap of the CIGS layer as compared to pure CIS, thus increasing the open-circuit voltage. In another point of view, gallium is added to replace as much indium as possible due to gallium's relative availability to indium.

Gallium Arsenide (GaAs) Multijunction
High-efficiency cells have been developed for special applications such as satellites and space exploration. These multijunction cells consist of multiple thin films produced using molecular beam epitaxy. A triple-junction cell, for example, may consist of the semiconductors: GaAs, Ge, and GaInP2. Each type of semiconductor will have a characteristic band gap energy which, loosely speaking, causes it to absorb light most efficiently at a certain color, or more precisely, to absorb electromagnetic radiation over a portion of the spectrum./Pol The semiconductors are carefully chosen to absorb nearly all of the solar spectrum, thus generating electricity from as much of the solar energy as possible.

GaAs multijunction devices are the most efficient solar cells to date, reaching a record high of 40.7% efficiency under solar concentration and laboratory conditions.[19] These devices use 20 to 30 different semiconductors layered in series. At the National Renewable Energy Laboratory, a new cell of area 0.26685 cm² will generate a power of 2.6 W. They estimate that this technology could eventually produce electricity at a mere 8–10 cents/kWh. This is similar to the price of electricity today. Thus, this breakthrough could ultimately result in increased consumer use of solar cells.

Light-Absorbing Dyes
Typically a ruthenium metalorganic dye (Ru-centered) is used as a monolayer of light-absorbing material. The dye-sensitized solar cell depends on a mesoporous layer of nanoparticulate titanium dioxide to greatly amplify the surface area (200-300 m²/g TiO2, as compared to approximately 10 m²/g of flat single crystal). The photogenerated electrons from the light absorbing dye are passed on to the n-type TiO2, and the holes are passed to an electrolyte on the other side of the dye. The circuit is completed by a redox couple in the electrolyte, which can be liquid or solid. This type of cell allows a more flexible use of materials, and is typically manufactured by screen printing, with the potential for lower processing costs than those used for bulk solar cells. However, the dyes in these cells also suffer from degradation under heat and UV light, and the cell casing is difficult to seal due to the solvents used in assembly. In spite of the above, this is a popular emerging technology with some commercial impact forecast within this decade.

Organic/Polymer Solar Cells
Organic solar cells are built from thin films (typically 100 nm) of an active, semiconductor layer. In polymer cells, the active layer typically consists of a conjugated electron donor polymer such as poly(p-phenylene-vinylene) or poly(3-hexylthiopene) (P3HT) in conjunction with a fullerene electron acceptor (such as PCBM or C60). In small molecule cells, phthalocyanine compounds or other planar, conjugated compounds are used as donors with fullerenes as acceptors. Energy conversion efficiencies achieved to date using conductive polymers are much lower than standard silicon cells, reaching about 12% for the most efficient polymer cells and about 8% for the most efficient small molecule cells. However, organic solar cells are cost competitive with commercial silicon cells, as they feature inexpensive, abundant materials and relatively easy manufacturing, without need of cleanroom technology or high temperature processing. They are also well suited to applications where mechanical flexibility and disposability are important.

Silicon
Silicon thin-films are mainly deposited by chemical vapor deposition (typically plasma-enhanced (PE-CVD)) from silane gas and hydrogen gas. Depending on the deposition's parameters, this can yield:


 * 1) Amorphous silicon (a-Si or a-Si:H)
 * 2) Protocrystalline silicon or
 * 3) Nanocrystalline silicon (nc-Si or nc-Si:H).

These types of silicon present dangling and twisted bonds, which results in deep defects (energy levels in the bandgap) as well as deformation of the valence and conduction bands (band tails). The solar cells made from these materials tend to have lower energy conversion efficiency than bulk silicon, but are also less expensive to produce. The quantum efficiency of thin film solar cells is also lower due to reduced number of collected charge carriers per incident photon.

Amorphous silicon has a higher bandgap (1.7 eV) than crystalline silicon (c-Si) (1.1 eV), which means it absorbs the visible part of the solar spectrum more strongly than the infrared portion of the spectrum. As nc-Si has about the same bandgap as c-Si, the two material can be combined in thin layers, creating a layered cell called a tandem cell. The top cell in a-Si absorbs the visible light and leaves the infrared part of the spectrum for the bottom cell in nanocrystalline Si.

Nanocrystalline Solar Cells
These structures make use of some of the same thin-film light absorbing materials but are overlain as an extremely thin absorber on a supporting matrix of conductive polymer or mesoporous metal oxide having a very high surface area to increase internal reflections (and hence increase the probability of light absorption).

Concentrating Pholtovoltaics
Concentrating photovoltaic systems use a large area of lenses or mirrors to focus sunlight on a small area of photovoltaic cells. If these systems use single or dual-axis tracking to improve performance, they may be referred to as Heliostat Concentrator Photovoltaics (HCPV). The primary attraction of CPV systems is their reduced usage of semiconducting material which is expensive and currently in short supply. Additionally, increasing the concentration ratio improves the performance of general photovoltaic materials and also allows for the use of high-performance materials such as gallium arsenide.

Silicon Processing
One way of reducing the cost is to develop cheaper methods of obtaining silicon that is sufficiently pure. Silicon is a very common element, but is normally bound in silica, or silica sand. Processing silica (SiO2) to produce silicon is a very high energy process - at current efficiencies, it takes over two years for a conventional solar cell to generate as much energy as was used to make the silicon it contains. More energy efficient methods of synthesis are not only beneficial to the solar industry, but also to industries surrounding silicon technology as a whole.

Thin-Film Processing
Thin-film solar cells use less than 1% of the raw material (silicon or other light absorbers) compared to wafer based solar cells, leading to a significant price drop per kWh. There are many research groups around the world actively researching different thin-film approaches and/or materials, however it remains to be seen if these solutions can generate the same space-efficiency as traditional silicon processing.

One particularly promising technology is crystalline silicon thin films on glass substrates. This technology makes use of the advantages of crystalline silicon as a solar cell material, with the cost savings of using a thin-film approach.

Another interesting aspect of thin-film solar cells is the possibility to deposit the cells on all kind of materials, including flexible substrates (PET for example), which opens a new dimension for new applications.

Polymer Processing
The invention of conductive polymers (for which Alan Heeger, Alan G. MacDiarmid and Hideki Shirakawa were awarded a Nobel prize) may lead to the development of much cheaper cells that are based on inexpensive plastics. However, all organic solar cells made to date suffer from degradation upon exposure to UV light, and hence have lifetimes which are far too short to be viable. The conjugated double bond systems in the polymers, which carry the charge, are always susceptible to breaking up when radiated with shorter wavelengths. Additionally, most conductive polymers, being highly unsaturated and reactive, are highly sensitive to atmospheric moisture and oxidation, making commercial applications difficult.

Nanoparticle Processing
Experimental non-silicon solar panels can be made of quantum heterostructures, eg. carbon nanotubes or quantum dots, embedded in conductive polymers or mesoporous metal oxides. In addition, thin films of many of these materials on conventional silicon solar cells can increase the optical coupling efficiency into the silicon cell, thus boosting the overall efficiency. By varying the size of the quantum dots, the cells can be tuned to absorb different wavelengths. Although the research is still in its infancy, quantum dot-modified photovoltaics may be able to achieve up to 42 percent energy conversion efficiency due to multiple exciton generation(MEG).

Transparent Conductors
Many new solar cells use transparent thin films that are also conductors of electrical charge. The dominant conductive thin films used in research now are transparent conductive oxides (abbreviated "TCO"), and include fluorine-doped tin oxide (SnO2:F, or "FTO"), doped zinc oxide (e.g.: ZnO:Al), and indium tin oxide (abbreviated "ITO"). These conductive films are also used in the LCD industry for flat panel displays. The dual function of a TCO allows light to pass through a substrate window to the active light absorbing material beneath, and also serves as an ohmic contact to transport photogenerated charge carriers away from that light absorbing material. The present TCO materials are effective for research, but perhaps are not yet optimized for large-scale photovoltaic production. They require very special deposition conditions at high vacuum, they can sometimes suffer from poor mechanical strength, and most have poor transmittance in the infrared portion of the spectrum (e.g.: ITO thin films can also be used as infrared filters in airplane windows). These factors make large-scale manufacturing more costly.

A relatively new area has emerged using carbon nanotube networks as a transparent conductor for organic solar cells. Nanotube networks are flexible and can be deposited on surfaces a variety of ways. With some treatment, nanotube films can be highly transparent in the infrared, possibly enabling efficient low bandgap solar cells. Nanotube networks are p-type conductors, whereas traditional transparent conductors are exclusively n-type. The availability of a p-type transparent conductor could lead to new cell designs that simplify manufacturing and improve efficiency.

Silicon Wafer Based Solar Cell
Despite the numerous attempts at making better solar cells by using new and exotic materials, the reality is that the photovoltaics market is still dominated by silicon wafer-based solar cells (first-generation solar cells). This means that most solar cell manufacturers are equipped to produce these type of solar cells. Therefore, a large body of research is currently being done all over the world to create silicon wafer-based solar cells that can achieve higher conversion efficiency without an exorbitant increase in production cost. The aim of the research is to achieve the lowest $/watt solar cell design that is suitable for commercial production.

Sliver Cells
Professor Andrew Blakers and Dr Klaus Weber, working at Australian National University and Origin Energy have developed a technique for slicing a single silicon wafer, which allows a significantly larger collector surface area from each wafer, compared to usual solar cells. The technique involves taking a silicon wafer, typically 1 to 2 mm thick, and making a multitude of parallel, transverse slices across the wafer, creating a large number of slivers that have a thickness of 50 micrometres and a width equal to the thickness of the original wafer. These slices are rotated 90 degrees, so that the surfaces corresponding to the faces of the original wafer become the edges of the slivers. The result is to convert, for example, a 150 mm diameter, 2 mm-thick wafer having an exposed silicon surface area of about 175 cm² per side into about 1000 slivers having dimensions of 100 mm x 2 mm x 0.1 mm, yielding a total exposed silicon surface area of about 2000 cm² per side. As a result of this rotation, the electrical doping and contacts that were on the face of the wafer are located the edges of the sliver, rather than the front and rear as is the case with conventional wafer cells. This has the interesting effect of making the cell sensitive from both the front and rear of the cell (a property known as bifaciality)