The necessities in Computer Design


 * control and data paths
 * pipeline design
 * cache design

Combinational Circuits

 * Bubble Pushing ([[Media:CArch.1.A.Bubble.20130327.pdf |pdf]])


 * See Understanding Arithmetic Circuits
 * - Carry Look-ahead Adder (CLA)
 * - Carry Save Adder (CSA)
 * - Prefix Adder (Prefix)* Multiplier
 * - Divider


 * ALU (Arithmetic Logical Unit)

Sequential Circuits

 * Types of Flip-Flops ([[Media:CDesign.1.A.FF.20130412.pdf |1A.pdf]])


 * FF Metastability ([[Media:CArch.Metastability.20131028.pdf |pdf]])
 * FF Min Max Timing Constraints ([[Media:CArch.MinMaxTiming.20131121.pdf |pdf]])
 * FF Clock Skew Timing Constraints ([[Media:CArch.ClockSkew.20131121.pdf |pdf]])


 * Synchronizer ([[Media:CArch.Synchronizer.20131216.pdf |pdf]])
 * Resolution Time Analysis ([[Media:CArch.Resolution.20131216.pdf |pdf]])

FSM (Finite State Machine)

 * FSM State Encoding
 * FSM Types : Mealy and Moore Machines
 * FSM Example ([[Media:CArch.2.A.FSMExample.20141018.pdf |pdf]])

ASM (Algorithmic State Machine)

 * ASM ([[Media:CDesign.1.A.ASM.20160507.pdf |pdf]])
 * - Reese's Lecture Note

One Hot Designs

 * One Hot Design ([[Media:CDsgn2.OneHot.20160509.pdf |pdf]])

Microprogramming

 * Microprogramming Design ([[Media:CDsgn2.uProg.20160513.pdf |pdf]])

Pipeline

 * Pipeline ([[Media:CDesign.4.A.Pipeline.20130621.pdf |4A.pdf]])
 * Latch Based Pipeline ([[Media:CDesign.4.B.LatchBasedPipeline.20130628.pdf |4B.pdf]])
 * Latch Time Borrow ([[Media:CDesign.4.C.LatchTimeBorrow.20130701.pdf |4C.pdf]])

Multiplier

 * Barrel Shifter ([[Media:CDesign.3.A.BShifter.20130524.pdf |3A.pdf]])
 * Booth Multiplier

Cache Memories

 * Content Addressable Memory ([[Media:CDsgn4.Cache.1.A.CAM.20160602.pdf |pdf]])
 * Address Partition ([[Media:CDsgn4.Cache.1.B.Address.20160602.pdf |pdf]])
 * Cache Mapping ([[Media:CDsgn4.Cache.1.C.Mapping.20160602.pdf |pdf]])

Interrupt

 * Interrupt ([[Media:CDsgn4.MMap.2.A.20160425.pdf |pdf]])

Memory Mapped IO

 * Memory Mapped IO ([[Media:CDsgn4.Interrupt.1.A.20160425.pdf |pdf]])

Intersystem Communication

 * Intersystem Communication ([[Media:CDsgn4.IComm.3.A.20160620.pdf |pdf]])

Implementation Techniques

 * ([[Media:SOC8.0.A.HW-SW-Overview.20160716.pdf |HW/SW Implementation Overview ]])

Implementation in Hardware
 * ([[Media:SOC8.1.A.RTLDesignExample.20160716.pdf |RTL Design Examples]])
 * ([[Media:SOC8.2.A.GateLevelDesignExample.20160716.pdf |Gate Level Design Examples]])
 * ([[Media:SOC8.3.A.TrLevelDesignExample.20160716.pdf |Transistor Level Design Examples]])

Implementation in Software
 * ([[Media:SOC8.4.A.BareMDesignExample.20160716.pdf |SW Implementation Without an OS (Bare Machine)]])
 * ([[Media:SOC8.5.A.RTOSDesignExample.20160718.pdf |SW Implementation with an RTOS]])


 * valvano

Tiny CPU Architecture Examples

 * Instruction Set ([[Media:CDsgn6.TinyCPU.2.A.ISA.20160511.pdf |pdf]])
 * Data Path ([[Media:CDsgn6.TinyCPU.2.B.DPath.20160502.pdf |pdf]])
 * Control Path ([[Media:CDsgn6.TinyCPU.2.C.CPath.20160427.pdf |pdf]])
 * FPGA Implementation ([[Media:CDsgn6.TinyCPU.2.D.Implement.20160513.pdf |pdf]])

C to HDL Exercises
go to [ Electrical_%26_Computer_Engineering_Studies ]
 * HDL Exercises ([[Media:ESys.3.A.ARM-ASM-Exercise.20160608.pdf |A.pdf]])