The necessities in Digital Design

Number Systems
 Binary Representation 
 * Binary Numbers ([[Media:DD1.1.A.BinaryNum.20130918.pdf|A.pdf]])
 * Hexadecimal Numbers ([[Media:DD1.2.A.HexaNum.20130918.pdf|A.pdf]])
 * Other Codes ([[Media:DD1.3.A.Coding.20140103.pdf|A.pdf]])

 Binary Arithmetic 
 * Binary Arithmetic ([[Media:DD1.4.A.BinaryArith.20150425.pdf|A.pdf]])
 * BCD Arithmetic ([[Media:DD1.5.A.BCDArith.20130918.pdf|A.pdf]])

 Interfacing Digital and Analog Signals 
 * Sampling and Quantization  ([[Media:DD1.10.A.SampleQuant.20150425.pdf|A.pdf]])
 * Digital-to-Analog Conversion ([[Media:DD1.8.A.DAC.20140208.pdf|A.pdf]])
 * Analog-to-Digital Conversion ([[Media:DD1.9.A.DAC.20140208.pdf|A.pdf]])

 C Program Examples 
 * Binary Numbers in C programs ([[Media:DD1.6.A.BNumInC.20140103.pdf|A.pdf]])
 * Binary Addition in C programs ([[Media:DD1.7.A.BArithInC.20140103.pdf|A.pdf]])


 * Helpful Wikipedia Pages ([[Media:DD.WP.NumberSystem.20130309.pdf|C.pdf]])


 * Floating Point Representations ([[Media:CDesign.5.A.FPoint.20140121.pdf|5A.pdf]])
 * See Floating Point Overview
 * See Offset Binary Overview
 * See Offset Binary & Sin / Cosine
 * See Offset Binary & ADC / DAC

Combinational Circuits
 Analysis 
 * Boolean Algebra ([[Media:DD2.A.1.BAlgebra.20130917.pdf|A1.pdf]])
 * Truth Tables ([[Media:DDD2.A.2.TTable.20130917.pdf|A2.pdf]])
 * K-Map ([[Media:DD2.A.3.KMap.20130925.pdf|A3.pdf]])
 * Design Examples ([[Media:DD2.A.4.CombEx.pdf|A4.pdf]])

 Components 
 * Decoder ([[Media:DD2.B.1.Decoder.20130928.pdf|B1.pdf]])
 * Encoder ([[Media:DD2.B.2.Encoder.20130917.pdf|B2.pdf]])
 * Multiplexer ([[Media:DD2.B.3.Multiplexer.20130928.pdf|B3.pdf]])
 * Adder ([[Media:DD2.B.4..Adder.20131007.pdf|B4.pdf]], [[Media:Fa.sch.20131002.pdf|fa.sch.pdf]], [[Media:Adder4.sch.20131002.pdf|adder4.sch.pdf]])

Sequential Circuits
 Analysis 
 * Latches and Flipflops ([[Media:DD3.A.1.LatchFF.20160308.pdf|A1.pdf]])
 * State Transition Table ([[Media:DD3.A.2.pdf|A2.pdf]])
 * FSM (Finite State Machine) ([[Media:DD3.A.3.FSM.20131030.pdf|A3.pdf]])


 * Metastability ([[Media:DD3.A.4.MetaState.20131030.pdf|A4.pdf]])
 * Flip-flop Timing ([[Media:DD3.A.5.FFTiming.20131104.pdf|A5.pdf]])
 * SR Latch Forbidden State ([[Media:DD3.A.5.ForbiddenState.20131030.pdf|A6.pdf]])
 * The Classic FF Design ([[Media:DD3.A.6.ClassicFF.20131126.pdf|A7.pdf]])
 * The Modern FF Design ([[Media:DD3.A.6.ClassicFF.20131204.2.pdf|A8.pdf]])

 Components 
 * Latches and Flip-flops ([[Media:DD3.B.1.LatchFF.20131008.pdf|B1.pdf]])
 * Registers ([[Media:DD3.B.2.Register.20150326.pdf|B2.pdf]], [[Media:Register.20131118.pdf|register.pdf]])
 * Counters ([[Media:DD3.B.2.Counter.20150420.pdf|B3.pdf]])

Array Devices
 Memory Arrays 
 * RAM
 * RAM Structure ([[Media:DD4.A.1.RAM.20131111.pdf|A.pdf]])
 * RAM Timing ([[Media:DD4.B.1.RAMTiming.20131130.pdf|B.pdf]])
 * FPGA RAM ([[Media:DD4.C.1.FPGARAM.20160513.pdf|C.pdf]])


 * ROM

 Logic Arrays  Synchronous SRAM Timing Asynchronous SRAM Timing DRAM Timing
 * PLA
 * PAL
 * PLD
 * FPGA
 * FPGA Structure
 * FPGA Configuration ([[Media:DD4.C.1.FPGAConf.20131130.pdf|B.pdf]])

FPGA Architectures CPLD & FPGA

RTL Design Techniques
 Design Methodology 

 Synthesis 

Logic Families and IOs

 * BJT Based
 * DTL (Diode-Transistor Logic)
 * TTL (Transistor-Transistor Logic)
 * ECL (Emitter-Coupled Logic)


 * MOS Based
 * CMOS (Complementary MOS)
 * Pseudo-nMOS
 * Transmission Gate
 * BiCMOS (Bipolr + CMOS)


 * Dynamic CMOS
 * Domino
 * Clocked-CMOS (C2MOS)


 * Modern I/O Standards
 * TTL and LVTTL (Low Voltage TTL)
 * CMOS and LVCMOS (Low Voltage CMOS)
 * SSTL (Stub Series Terminated Logic)
 * HSTL (High Speed Tranceiver Logic)
 * LVDS (Low Voltage Differential Signaling)


 * Wikipedia Pages for Logic Families ([[Media:Logic Families.wiki.20140812.pdf|A.pdf]])

See also   

go to [ Electrical_%26_Computer_Engineering_Studies ]

Old
Until 2011.12 '''Chapter 1. Binary Numbers'''
 * 1.1 Binary Numbers([[Media:BinaryNumbers.1.A.pdf|pdf]])

 Minterm, Maxterm, HW 
 * 1.1 Lecture01([[Media:DigitalDesign.20110922.pdf|pdf]])

 Overflow HW 
 * Overflow Table([[Media:Overflow table.20110924.pdf|pdf]])

 K-Map 
 * K-Map([[Media:DigitalDesign.20110926.pdf|pdf]])

 Binary Adder 
 * Binary Adder (C, S) ([[Media:DigitalDesign.20110929.pdf|pdf]])
 * Overflow detection circuit (V) ([[Media:HW Overflow20111001.pdf|pdf]])

 BCD to Ex3 Code Coversion, Dont' Care 
 * BCD to Ex3 Code Conversion ([[Media:DigitalDesign.20111006.pdf|pdf]])

 Prime Implicant, Dont' Care 
 * Prime Implicant, Don't Care ([[Media:DigitalDesign.20111010.pdf|pdf]])
 * HW 3.6 - explain the method of combining 0's and X's

 Multiplexer / Demultiplexer 
 * Multiplexer ([[Media:DigitalDesign.20111024.pdf|pdf]])
 * HW (TBD)

 Flip Flop / Latch   Counter   Memory 
 * FF & Latch ([[Media:DigitalDesign.20111027.pdf|pdf]])
 * FF & Latch HW ([[Media:DigitalDesign (HW).20111027.pdf|pdf]])
 * Gated D Latch & Master-Slave D FlipFlop ([[Media:DigitalDesign.20111031.pdf|pdf]])
 * HW (Forbidden state and Indeterminate state) ([[Media:DigitalDesign (HW).20111102.pdf|pdf]]) (note in #2, S' R' instead of S R)
 * Classical Edge Triggered D FlipFlop ([[Media:DigitalDesign.20111112.pdf|pdf]])
 * HW (addition in SW and HW) ([[Media:DigitalDesign (HW).20111112.pdf|pdf]])
 * FSM1 ([[Media:DigitalDesign.FSM1.20111117.pdf|pdf]])
 * FSM2 ([[Media:DigitalDesign.FSM2.20111117.pdf|pdf]])
 * HW (FSM Waveforms) ([[Media:DigitalDesign (HW).20111118.pdf|pdf]])
 * Sychronous Counter ([[Media:DigitalDesign.20111121.pdf|pdf]])
 * Ripple Counter, Multiplexer, Tri-state buffer([[Media:DigitalDesign.20111124.pdf|pdf]])
 * Register ([[Media:DigitalDesign.register.20111201.pdf|pdf]])
 * Timing ([[Media:DigitalDesign.timing.20111201.pdf|pdf]])
 * HW (Multiplexer, Shift Register) ([[Media:DigitalDesign (HW).20111201.pdf|pdf]])
 * Universal Shift Register, Memory Cell ([[Media:DigitalDesign.20111206.pdf|pdf]])
 * HW (Bit Serial Adder) ([[Media:DigitalDesign (HW).20111206.pdf|pdf]])
 * Memory ([[Media:DigitalDesign.20111208.pdf|pdf]])

 Comparator, Multiplier  Multiplexer based design method 
 * Comparator, Multiplier ([[Media:DigitalDesign.20111219.spread.pdf|1.pdf]], [[Media:DigitalDesign.20111219.draw.pdf|2.pdf]])
 * Multiplexer Design Method ([[Media:DigitalDesign.20111221.spread.pdf|1.pdf]], [[Media:DigitalDesign.20111221.draw.pdf|2.pdf]])

midterm result ([[Media:MidReult.20111027.pdf|pdf]])


 * Edge Triggered Flip Flop ([[Media:EdgeTrigFF.20111224.pdf|pdf]])
 * FF Timing ([[Media:FFTiming.20111203.pdf|pdf]])

Until 2013.07

 Number Systems 
 * Binary Numbers ([[Media:DD.1.A.BinNum.20130309.pdf|A.pdf]])
 * Hexadecimal Numbers ([[Media:DD.1.B.HexaNum.20130417.pdf|B.pdf]])
 * Numbers in C programs ([[Media:DD.1.C.CNum.20130309.pdf|C.pdf]])
 * Codes ([[Media:DD.1.D.Coding.20130319.pdf|pdf]])


 * Helpful Wikipedia Pages ([[Media:DD.WP.NumberSystem.20130309.pdf|pdf]])

 Combinational Circuits 
 * Truth Tables and Boolean Functions ([[Media:DD.2.A.TTable.20130325.pdf|2A.pdf]])
 * K-Map ([[Media:DD.2.A.KMap.20130329.pdf|2B.pdf]])
 * Binary Addition in C ([[Media:DD.2.C.BAinC.20130329.pdf|2.C.pdf]])
 * Binary Arithmetic ([[Media:DD.2.D.BAri.2013.pdf|2.D.pdf]])
 * Boolean Algebra ([[Media:DD.2.E.BAlgebra.20130419.pdf|2.E.pdf]])

 Sequential Circuits 
 * Latches and Flip-flops ([[Media:DD.3.A.LatchFF.20130413.pdf|3A.pdf]])
 * FSM (Finite State Machine) ([[Media:DD.3.B.FSM.20130417.pdf|3B.pdf]])
 * SR Latch Forbidden State ([[Media:DD.3.C.FState.20130413.pdf|3C.pdf]])
 * Flip-flop Timing ([[Media:DD.3.D.Timing.20130413.pdf|3D.pdf]])
 * Metastability ([[Media:DD.3.E.MetaState.20130628.pdf|3E.pdf]])

See also "The necessities in Computer Design" "The necessities in Computer Architecture"