The necessities in SOC Design

Overview

 * SoC in the wikipedia pages ([[Media:0.Overview.SoC.20160304.pdf.pdf |pdf]])

Fabrication of VLSI Circuits

 * Fabrication in the wikipedia pages ([[Media:1.Fabrication.20130218.pdf |pdf]])
 * Wafer ([[Media:SOC.1.A.Wafer.20130430.pdf |pdf]])
 * Mask ([[Media:SOC.1.B.Mask.20130320.pdf |pdf]])
 * Package ([[Media:SOC.1.C.Package.20130320.pdf |pdf]])
 * Test ([[Media:SOC.1.D.Test.20130320.pdf |pdf]])


 * CMOS Fabrication ([[Media:1.SOC.2.B.CMOS.Process.20130430.pdf |pdf]])

Device Level Design

 * MOSFET Transistor ([[Media:B1.SOC.2.A.CMOS.Transistor.20160324.pdf |pdf]])
 * CMOS Inverter ([[Media:B1.SOC.2.B.Device.Inverter.20160406.pdf |pdf]])


 * Digital Implementation ([[Media:1.SOC.2.C.CMOS.Digital.20130318.2.pdf |pdf]]) - ASIC, FPGA
 * Analog Implementation ([[Media:1.SOC.2.D.CMOS.Analog.20130320.pdf |pdf]]) - Linear IC, Power IC, RF IC, Mixed Signal IC

Performance Metrics

 * Device R, C ([[Media:1.SOC.2.E.Device.RC.20160407.pdf |pdf]])
 * Device Size ([[Media:1.SOC.2.G.Device.Size.20160401.pdf |pdf]])
 * Device Delay ([[Media:1.SOC.2.F.CMOS.Delay.20160407.pdf |pdf]])
 * Device Power ([[Media:1.SOC.2.H.CMOS.Power.20160404.pdf |pdf]])

Device Level Design Tools

 * Spice Simulator
 * VLSI CAD tools - Layout, Floorplanning, Placement and Routing, Physical Verification (LVS/DRC/ERC)

Transistor Level Design

 * Combinational Designs ([[Media:1.SOC.3.A.Trans.Combinational.20160315.pdf |pdf]])
 * Sequential Designs ([[Media:1.SOC.3.B.Trans.Sequential.20160315.pdf |pdf]])
 * Subsystem
 * Arithmetic Subsystem ([[Media:1.SOC.3.G.Trans.Adder.20160315.pdf |pdf]])
 * Memory Array Subsystem ([[Media:1.SOC.3.H.Trans.Memory.20160315.pdf |pdf]])
 * Logic Array Subsystem

Performance Metric

 * Gate Area ([[Media:1.SOC.3.F.Trans.Area.20160318.pdf |pdf]])
 * Gate Delay ([[Media:1.SOC.3.D.Trans.Delay.20160318.pdf |pdf]])
 * Gate Power ([[Media:1.SOC.3.E.Trans.Power.20160325.pdf |pdf]])

Design Issues

 * Clock
 * PLL & DLL
 * I/O

Transistor Level Design Tools

 * Spice

Gate Level Design

 * Combinational Designs ([[Media:1.SOC.4.A.Gate.Combi.20160322.pdf |pdf]])
 * Sequential Designs ([[Media:1.SOC.4.B.Gate.Sequential.20160315.pdf |pdf]])
 * Subsystem
 * Arithmetic Subsystem ([[Media:1.SOC.4.G.Gate.Adder.20160315.pdf |pdf]])
 * Memory Array Subsystem ([[Media:1.SOC.4.H.Gate.Memory.20160523.pdf |pdf]])
 * Logic Array Subsystem

Performance Metric

 * Gate Count
 * Path Delay ([[Media:1.SOC.4.D.Gate.PathDelay.20160325.pdf |pdf]])
 * Switch Activity ([[Media:1.SOC.4.D.Gate.Power.20160325.pdf |pdf]])

Design Issues

 * Static Timing Analysis
 * Scan and Boundary Scan Cells
 * Formal Verification

Gate Level Design Tools

 * Verilog
 * VHDL
 * Static Timing Analysis
 * Formal Verification

RTL Level Design

 * Register ([[Media:1.SOC.4.A.Register.20160308.pdf |pdf]])
 * FSM ([[Media:1.SOC.4.B.FSM.20160308.pdf |pdf]])
 * One Hot Controller
 * Pipeline ([[Media:1.SOC.5.D.Pipeline.20160319.pdf |pdf]])

Performance Metric

 * Estimation of
 * Gate Count
 * Critical Path
 * Power
 * Latency
 * Throughput

Design Issues

 * Partitioning and Coding Style
 * Constraining Designs
 * Optimizing Designs
 * Design for Test (DFT)
 * Pre-layout & Post-layout Simulation

RTL Design Tools

 * Verilog
 * VHDL
 * Logic Synthesis

Background: Tiny CPU Examples

 * ([[Media:CDsgn6.TinyCPU.2.A.ISA.20160502.pdf |Instruction Set]])
 * ([[Media:CDsgn6.TinyCPU.2.B.DPath.20160428.pdf |Data Path]])
 * ([[Media:CDsgn6.TinyCPU.2.C.CPath.20160427.pdf |Control Path]])


 * Processors ([[Media:7.SOC.1.A.Processor.20160513.pdf |pdf]])
 * Memories ([[Media:7.SOC.1.B.Memory.20160516.pdf |pdf]])
 * - Cache Memory
 * Readings ([[Media:SOC.Cache.Reading.20160614.pdf |pdf]])
 * Cache Note ([[Media:SOC.Cache.20160530.pdf |pdf]])
 * See also Content Addressable Memory ([[Media:CDsgn4.Cache.1.A.CAM.20160602.pdf |pdf]]), Address Partition ([[Media:CDsgn4.Cache.1.B.Address.20160602.pdf |pdf]]), Cache Mapping ([[Media:CDsgn4.Cache.1.C.Mapping.20160602.pdf |pdf]])


 * - Virtual Memory
 * Readings ([[Media:SOC.VMem.20160604.pdf |pdf]])


 * - DRAM
 * Readings ([[Media:SOC.DRAM.20160603.pdf |pdf]])
 * See also RAM Structure ([[Media:DD4.A.1.RAM.20131111.pdf |pdf]]), RAM Timing ([[Media:DD4.B.1.RAMTiming.20131130.pdf |pdf]]), FPGA RAM ([[Media:DD4.C.1.FPGARAM.20160513.pdf |pdf]])


 * Interconnecting Buses
 * - AMBA AHB & APB
 * Readings ([[Media:SOC.AMBA.20160617.pdf |pdf]])


 * CISC, RISC, VLIW, Dataflow ([[Media:SOC6.Arch.1.A.20160510.pdf |1.pdf]])
 * CPU, DSP, GPU, NPU ([[Media:SOC6.Arch.2.A.20160510.pdf |2.pdf]])
 * MCU, ASIP, TTA ([[Media:SOC6.Arch.3.A.20160510.pdf |3.pdf]])

Design Issues

 * Memory Hierarchy
 * Storage and I/O
 * Instruction Level Parallelism
 * Data Level Parallelism
 * Thread Level Parallelism

Design Tools

 * ADL (Architecture Design Language)
 * - LISA, EXPRESSION, nML, ArchC


 * SystemC TLM (Transaction Level Modeling)

System Level Design

 * IP : OCP-IP, OpenCore

Typical SOC's

 * Embedded System
 * MPSOC
 * NoC

Design Issues

 * Transaction Level Modeling
 * Hardware Software Partition
 * Hardware Software Co-simulation
 * Integration of Hardware IP Blocks
 * Integration of Software IP Modules
 * FPGA Based Emulation Platform

Design Tools

 * High-Level Synthesis
 * HVL (High-Level Verification Language)
 * - SystemC Verifcation (SCV) (See "SystemC programming in plain view")
 * - SystemVerilog


 * Mixed Signal
 * - VHDL-AMS
 * - Verilog-AMS
 * - SystemC-AMS

HW/SW Design Examples : Traffic Controller Design

 * HW/SW Implementation Overview ([[Media:SOC8.0.A.HW-SW-Overview.20160716.pdf |pdf]])

Implementation in Hardware
 * RTL Design Examples ([[Media:SOC8.1.A.RTLDesignExample.20160716.pdf |pdf]])
 * Gate Level Design Examples ([[Media:SOC8.2.A.GateLevelDesignExample.20160716.pdf |pdf]])
 * Transistor Level Design Examples ([[Media:SOC8.3.A.TrLevelDesignExample.20160716.pdf |pdf]])

Implementation in Software
 * SW Implementation Without an OS (Bare Machine)
 * - Overview ([[Media:SOC8.4.A.BareMDesignExample.20160716.pdf |pdf]])
 * - Micro-controller Programming ([[Media:SOC8.4.B.MicroController.20200417.pdf |pdf]])


 * SW Implementation with an RTOS ([[Media:SOC8.5.A.RTOSDesignExample.20160718.pdf |pdf]])

RTL / Logic Level Design

 * Logic Synthesis
 * Logic Simulation
 * Logic Timing Verification
 * Logic Power Verification
 * Test Synthesis
 * Test Verification
 * Testbench
 * Code Coverage
 * Equivalence Check
 * Timing Verification
 * Design Constraint
 * STA (Static Timing Analysis)
 * Scan Chain
 * Back Annotation
 * ATPG (Automatic Test Pattern Generation)


 * See also SoC Design and Modelling Greave's Tutorial

Physical Design

 * Floorplanning
 * Placement
 * Routing
 * Power Network
 * Clock Distribution
 * Physical Verification
 * DRC (Design Rule Check)
 * DV (Design Verification)
 * GV (Geometry Verification)
 * LVS (Layout Versus Schematic)
 * SV (Schematic Verification)

Test

 * Design For Test
 * ATPG (Automatic Test Pattern Generation)
 * Analog and Mixed Signal Test
 * JTAG (Joint Test Action Group) IEEE 1149.1
 * Embedded Core Test IEEE 5000
 * test access mechanisms (TAMs)
 * Core test language (CTL)

Logical Verification

 * Assertion Based Verification
 * Transaction Level Models
 * Formal Property Verification

2016 Spring Class

 * Some useful links in VLSI design ([[Media:SOC.0.B.Link.20160412.pdf |1.pdf]], [[Media:Conents.pdf |2.pdf]])
 * SystemC Projects ([[Media:SOC.0.C.Proj.20160617.pdf |1.pdf]]) updated
 * SystemC Installation Guide ([[Media:SOC.0.C.Proj.SystemC.20160616.pdf |pdf]])
 * OpenRISC ISS or1ksim Installation Guide ([[Media:SOC.0.C.Proj.or1ksim.20160617.pdf |pdf]])

go to [ Electrical_%26_Computer_Engineering_Studies ]
 * HW#1 ([[Media:HW-1.20160411.pdf |pdf]])
 * HW#2 ([[Media:HW-2.20160412.pdf |pdf]])
 * HW#3 ([[Media:HW-3.20160416.pdf |pdf]])
 * HW#4 ([[Media:HW-4.20160412.pdf |pdf]])
 * HW#6 ([[Media:HW-6.Cache.20160610.pdf |pdf]])
 * HW#7 ([[Media:HW-7.Memory.20160609.pdf |pdf]]) - Pipeline Burst EDO DRAM
 * finallist ([[Media:content2.20160615.pdf |pdf]])