Understanding FPGA Design

Programmable Logic Devices

 * PLA
 * PAL
 * GAL
 * CPLD
 * FPGA

FPGA Architectures

 * Basic structure of FPGAs ([[Media:FPGA.1.A.Structure.20190206.pdf |pdf]])
 * FPGA based on SRAMs ([[Media:FPGA.2.A.SRAMbased.20190206.pdf |pdf]])
 * FPGA based on ROMs with anti-fuses ([[Media:FPGA.3.A.ROMbased.20190211.pdf |pdf]])
 * FPGA based on Non-volatile Memories ([[Media:FPGA.4.A.NonVolatile.20190214.pdf |pdf]])
 * Features of FPGAs

Circuit Level Characteristics

 * Logic Cell Circuit
 * IO Cell Circuit
 * Interconnect Circuit

FPGA Development Phases

 * Design
 * Simulation
 * Synthesis
 * Implementation ([[Media:FPGA.Implementation.20160802.pdf |pdf]])
 * Programming

Clocking Scheme

 * Clock Control
 * Clock Domain
 * Reset Signals
 * Xilinx DCM & 2-phase clock, Contraining technique
 * Xilinx XPower, Power and Energy Aware Design?

Using ROM

 * VHDL Example Code ( [[Media:rom.20131107.pdf |pdf]] )

Latch based design

 * Latch in FGPA ( [[Media:FPGA.1.A.Latch.20150218.pdf |pdf]] )

Dual Edge Triggered Flip Flop based design
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