Understanding VLSI Design

CMOS VLSI Design

 * Introduction ([[Media:Introduction.20150910.pdf |pdf]])

Device

 * MOSFET-1 : Capacitors ([[Media:MOSFET.Note.H.1.20160227.pdf |pdf]])
 * MOSFET-2 : Operation Modes ([[Media:MOSFET.Note.H.2.20160227.pdf |pdf]])
 * MOSFET-3 : Capacitance Types ([[Media:MOSFET.Note.H.3.20160407.pdf |pdf]])
 * MOSFET-4 : Body Effect, Latchup ([[Media:MOSFET.Note.H.4.20170308.pdf |pdf]])
 * MOSFET-5 : Energy Band Diagrams ([[Media:MOSFET.Note.H.5.20151218.pdf |pdf]])
 * ([[Media:EnergyBand.1.A.20150923.pdf |Energy Band]])


 * Inverter-1 : Inverter, VTC, Noise Margin ([[Media:Inverter.Note.H.1.20170329.pdf |pdf]])
 * Inverter-2 : nMOS Linear Model, nMOS Resistance, nMOS Capacitance ([[Media:Inverter.Note.H.2.20160227.pdf |pdf]])
 * Inverter-3 : Inverter Fall Delay & Rise Delay, Propagation Delay, and Gate Delay ([[Media:Inverter.Note.H.3.20151218.pdf |pdf]])
 * PassTr : Pass Transistor ([[Media:PassTr.Note.H.1.20151219.pdf |pdf]])

Spice Model & Simulation

 * Spice ([[Media:Spice.Note.H.1.20151014.pdf |pdf]])

Layout & Simulation

 * Electric (Static Free Software)
 * LT Spice (Linear Technology)

Delay
Logic Level Delay Overview
 * Background ([[Media:DelayBackground.1.A.20151020.pdf |pdf]])
 * RTL Timing ([[Media:DelayRTLTiming.1.A.20151020.pdf |pdf]])
 * Delay Models in Verilog ([[Media:DelayModel.Note.H.1.20151201.pdf |pdf]])
 * Delay Annotation and SDF ([[Media:SDF.Note.H.1.20151201.pdf |pdf]])

See Timing Characterization

CMOS Level Delay
 * Delay-1 : Transistor Sizing ([[Media:DelayCMOS.H.1.TrSizing.20160905.pdf |pdf]])
 * Delay-2 : Logical Effort ([[Media:DelayCMOS.H.2.LEffort.20160826.pdf |pdf]])
 * Delay-3 : Logical Effort Applications ([[Media:DelayCMOS.H.3.LEffortApp.20160919.pdf |pdf]])
 * Delay-4 : Device Delay ([[Media:DelayCMOS.H.4.Device.20161107.pdf |pdf]])
 * Delay-5 : Inverter Chain Delay ([[Media:DelayCMOS.H.5.InvChain.20161202.pdf |pdf]])
 * Delay-6 : Multistage Delay ([[Media:DelayCMOS.H.6.MultiStage.20161231.pdf |pdf]])
 * Delay-7 : Elmore Delay ([[Media:DelayCMOS.H.7.Elmore.20170117.pdf |pdf]])
 * Delay-8 : Delay Model ([[Media:DelayCMOS.H.8.Model.20170211.pdf |pdf]])
 * Delay-9 : Wire Delay ([[Media:DelayCMOS.H.9.Wire.20170121.pdf |pdf]])
 * Delay-A : Logical Effort and Gate Sizing

Power
Logic Level Power Overview CMOS Level Power
 * Power-1 ([[Media:Power.Note.H.1.20160405.pdf |pdf]]) : Power

Simple Logic Gate Design
NAND Gate Design
 * NAND ([[Media:NAND.1.A.20171009.pdf |pdf]])

NOR Gate Design
 * NOR ([[Media:NOR.1.A.20170829.pdf |pdf]])

Combinational Circuit Design
Logic Level Combinational Circuit Design Overview CMOS Level Combinational Circuit Design
 * Background ([[Media:CombBackground.1.A.20151106.pdf |pdf]])
 * Combinational-1 : Pull Up Network, Pull Down Network, AOI, OAI ([[Media:Combi-1.Note.H.1.20151118.pdf |pdf]])
 * Combinational-2 : Decoder, Mux, Tristate Inv ([[Media:Combi-2.Note.H.2.20151111.pdf |pdf]])
 * Combinational-3 : Standard Cell, Design Flow ([[Media:Combi-3.Note.H.3.20151111.pdf |pdf]])

Sequential Circuit Design
Logic Level Sequential Circuit Design Overview CMOS Level Sequential Circuit Design
 * Background ([[Media:SeqBackground.1.A.20151106.pdf |pdf]])
 * Sequential Timing ([[Media:SequentialTiming.1.A.20151106.pdf |pdf]])
 * FSM Examples ([[Media:FSMExample.1.A.20151106.pdf |pdf]])
 * Sequential-1 : Modern Latch & Flipflop([[Media:Seq-1.Note.H.1.20151215.pdf |pdf]])
 * Sequential-2 : Classical Latch & Flipflop([[Media:Seq-2.Note.H.2.20151215.pdf |pdf]])
 * Sequential-3 : Latch & Flipflop Timing Constraints([[Media:Seq-3.Note.H.3.20151215.pdf |pdf]])
 * Sequential-4 : Enable, Reset, Set ([[Media:Seq-4.Note.H.4.20151215.pdf |pdf]])

Other MOS Logic Family Design

 * Static-1 : Pseudo-nMOS, Transmission Gate ([[Media:Static-1.Note.H.1.20151215.pdf |pdf]])
 * Static-2 : Skewed Inverters, Ratioed Logic ([[Media:Static-2.Note.H.2.20151215.pdf |pdf]])
 * Dynamic-1 : Footed, Unfooted, Domino Logic ([[Media:Dynamic-1.Note.H.1.20151215.pdf |pdf]])
 * Dynamic-2 : Logical Effort of Dynamic Logic Gates ([[Media:Dynamic-2.Note.H.2.20151215.pdf |pdf]])

Datapath Design
Ripple Carry Adder
 * Logic Level Analysis ([[Media:VLSI.Arith.1.A.RCA.20151113.pdf |pdf]])
 * VHDL Implementations ([[Media:adder.rca.20140313.pdf |pdf]])
 * CMOS Level Analysis ([[Media:RCA.Note.H.1.20151215.pdf |pdf]])

Carry-Lookahead Adder
 * Logic Level Analysis ([[Media:VLSI.Arith.1.A.CLA.20151113.pdf |pdf]])
 * VHDL Implementations ([[Media:adder.cla.20140313.pdf |pdf]])
 * CMOS Level Analysis ([[Media:CLA.Note.H.1.20151215.pdf |pdf]])

Carry Save Adder
 * Logic Level Analysis ([[Media:VLSI.Arith.1.A.CSave.20151209.pdf |pdf]])
 * VHDL Implementations
 * CMOS Level Analysis

Multiplier
 * CMOS Level Analysis ([[Media:Mult.Note.H.1.20151130.pdf |pdf]])
 * Array Multiplier ([[Media:VLSI.Arith.1.A.Mult.20151209.pdf |pdf]])
 * Barrel Shifter ([[Media:Arith.BShfiter.20151207.pdf  |pdf]])
 * Other Multipliers ([[Media:Mult-2.Note.H.2.20151215.pdf |pdf]])

Memory Array Subsystem Design
Logic Level Overview CMOS Level
 * Background ([[Media:MemBackground.1.A.20151201.pdf |pdf]])
 * DRAM Memory ([[Media:CO.DRAM.H1.20151211.pdf |pdf]])
 * For DRAM, SDRAM, DDR, see B. Jacob's lecture notes on umd
 * For a simple computer architecture, see Tiny CPU example
 * [[Media:CArch.5.A.TinyCPU.20141028.pdf | TinyCPU Architecutre Timing Diagrams]]
 * SRAM ([[Media:SRAM.Note.H.1.20151217.pdf |pdf]])
 * DRAM ([[Media:DRAM.Note.H.1.20151217.pdf |pdf]])
 * Cache

Logic Array Subsystem Design
Logic Level Overview CMOS Level

Package
See also
 * Understanding CMOS Design
 * The necessities in Digital Design ‎
 * The necessities in Computer Design ‎
 * The necessities in Computer Architecture ‎
 * The necessities in Computer Organization ‎
 * Understanding Arithmetic Circuits ‎

go to [ Electrical_%26_Computer_Engineering_Studies ]
 * Understanding Low Power Design
 * [Understanding Arithmetic Circuits]] ‎
 * Understanding FPGA Design