User:1sfoerster/enes245/fall2014/wikibookFPGAimprove

=Problem= Wikibook VHDL for FPGA Design belongs on wikiversity and it is general in nature. Need to re-write specifically for papilio with logic start mega wing.

=Conceive= Add these sections to each of the VHDL examples in the wikibook:
 * Link to original wikibook entry
 * logisim gate diagram (with link to logisim circuit and uploaded screen shot)
 * VHDL code
 * Associated constraints file
 * VHDL test file
 * Expected test results graphic

=Design= Slit up into these groups just like the wikibook


 * 1) Decoder
 * 2) Multiplexer
 * 3) /Priority Encoder/
 * 4) /4-Bit Adder/
 * 5) /4-Bit Multiplier/
 * 6) /4-Bit ALU/


 * 1) /D Flip Flop/
 * 2) /T Flip Flop/
 * 3) /JK Flip Flop/
 * 4) /4-Bit Binary Counter with Parallel Load/
 * 5) /4-Bit BCD Counter with Clock Enable/
 * 6) /4-Bit Shift Register/
 * 7) /4-Bit Johnson Counter with Reset/


 * 1) /State-Machine Design Example Asynchronous Counter/
 * 2) /State-Machine Design Example Serial Parity Generator/

=Implement= Expand the above

=Operate= Example of how the above can be used in a project =Demo= presentation =Next Steps=