User:1sfoerster/enes245/spring/8-notes

=Problem= Getting the Papilio to play a sound is simple enough. Feed 1's and 0's to a DAC module connected to an audio output and voila! But a single sound is boring. What if we want the Papilio to play multiple sounds simultaneously? That is the goal of this project. As for Spring 2015, The updated main goal is to make the papilio play the Musical Scale's 8-notes.

=Conceive= Initial inspiration for this project was the similarity of utilizing modules when coding in VHDL and the modules used with a modular synthesizer. In theory, one could use multiple Papilios communicating with each other, each with a specified purpose, and create a modular synthesizer.

Scaling down this idea to just one module, I set my eyes on creating an 8 channel audio multiplexer making use of Time-division multiplexing

=Design=

-- -- Name: Farouq Narmouq -- Originally developed by Christopher Carreras -- Redesigned and updated by Farouq Narmouq -- Date: 11 May 2015 -- Module Name: AudioMultiplexer - Behavioral (Main) -- Target Devices: Papilio 250K -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity AudioMultiplexer is   Port ( clk 				: in  STD_LOGIC;   --      audiochannel 	: out  STD_LOGIC_VECTOR (1 downto 0);           A 					: in  STD_LOGIC_VECTOR(7 downto 0);           B 					: in  STD_LOGIC_VECTOR(7 downto 0);           C 					: in  STD_LOGIC_VECTOR(7 downto 0);           D 					: in  STD_LOGIC_VECTOR(7 downto 0);			  E 					: in  STD_LOGIC_VECTOR(7 downto 0);			  F 					: in  STD_LOGIC_VECTOR(7 downto 0);			  G 					: in  STD_LOGIC_VECTOR(7 downto 0);			  CMid				: in  STD_LOGIC_VECTOR(7 downto 0);   --      counter 			: in  STD_LOGIC_VECTOR (29 downto 0);           audiosource		: in  STD_LOGIC_VECTOR (7 downto 0); -- these will be the switches			  dout				: out STD_LOGIC_VECTOR (7 downto 0)); end AudioMultiplexer;

architecture Behavioral of AudioMultiplexer is	signal 	seconds			:	STD_LOGIC_VECTOR(2 downto 0)	:= (others=>'0'); signal	count				:	STD_LOGIC_VECTOR(29 downto 0)	:= (others=>'0'); signal	wave1				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave2				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave3				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave4				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave5				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave6				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave7				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave8				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); begin

audiomux_proc: process(clk) begin if rising_edge(clk) then count <= count + 1; if (count = 319) then seconds <= seconds + 1; count <= (others=> '0'); end if; --1			if (audiosource(0) = '1') then wave1 <= C;			else wave1 <= (others=>'0'); end if; --2			if (audiosource(1) = '1') then wave2 <= B;			else wave2 <= (others=>'0'); end if; --3			if (audiosource(2) = '1') then wave3 <= A;			else wave3 <= (others=>'0'); end if; -4			if (audiosource(3) = '1') then wave4 <= G;			else wave4 <= (others=>'0'); end if; -5			if (audiosource(4) = '1') then wave5 <= F;			else wave5 <= (others=>'0'); end if; -6			if (audiosource(5) = '1') then wave6 <= E;			else wave6 <= (others=>'0'); end if; -7			if (audiosource(6) = '1') then wave7 <= D;			else wave7 <= (others=>'0'); end if; -8			if (audiosource(7) = '1') then wave8 <= CMid; else wave8 <= (others=>'0'); end if; ---			CASE seconds IS				WHEN "000" => dout <= wave1; --A WHEN "001" => dout <= wave2; --B WHEN "010" => dout <= wave3; --C WHEN "011" => dout <= wave4; --D WHEN "100" => dout <= wave5; --E WHEN "101" => dout <= wave6; --F WHEN "110" => dout <= wave7; --G WHEN OTHERS => dout <= wave8; --A END CASE; end if; end process;

end Behavioral; -- --

--Inst_dac8

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dac8 is	Port ( Clk : in STD_LOGIC;			 Data : in STD_LOGIC_VECTOR (7 downto 0);			 PulseStream : out STD_LOGIC); end dac8;

architecture Behavioral of dac8 is	signal sum : STD_LOGIC_VECTOR (8 downto 0); begin PulseStream <= sum(8); process (clk, sum) begin if rising_edge(Clk) then sum <= ("0" & sum(7 downto 0)) + ("0" &data); end if; end process; end Behavioral; --- ---

--

-- --Inst_AudioMultiplexer -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity AudioMultiplexer is   Port ( clk 				: in  STD_LOGIC;   --      audiochannel 	: out  STD_LOGIC_VECTOR (1 downto 0);           A 					: in  STD_LOGIC_VECTOR(7 downto 0);           B 					: in  STD_LOGIC_VECTOR(7 downto 0);           C 					: in  STD_LOGIC_VECTOR(7 downto 0);           D 					: in  STD_LOGIC_VECTOR(7 downto 0);		   E 					: in  STD_LOGIC_VECTOR(7 downto 0);		   F 					: in  STD_LOGIC_VECTOR(7 downto 0);		   G 					: in  STD_LOGIC_VECTOR(7 downto 0);		   CMid				: in  STD_LOGIC_VECTOR(7 downto 0);   --      counter 			: in  STD_LOGIC_VECTOR (29 downto 0);           audiosource		: in  STD_LOGIC_VECTOR (7 downto 0); -- these will be the switches		   dout				: out STD_LOGIC_VECTOR (7 downto 0)); end AudioMultiplexer;

architecture Behavioral of AudioMultiplexer is	signal 	seconds			:	STD_LOGIC_VECTOR(2 downto 0)	:= (others=>'0'); signal	count				:	STD_LOGIC_VECTOR(29 downto 0)	:= (others=>'0'); signal	wave1				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave2				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave3				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave4				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave5				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave6				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave7				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); signal	wave8				: 	STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); begin

audiomux_proc: process(clk) begin if rising_edge(clk) then count <= count + 1; if (count = 319) then seconds <= seconds + 1; count <= (others=> '0'); end if; --1			if (audiosource(0) = '1') then wave1 <= C;			else wave1 <= (others=>'0'); end if; --2			if (audiosource(1) = '1') then wave2 <= B;			else wave2 <= (others=>'0'); end if; --3			if (audiosource(2) = '1') then wave3 <= A;			else wave3 <= (others=>'0'); end if; -4			if (audiosource(3) = '1') then wave4 <= G;			else wave4 <= (others=>'0'); end if; -5			if (audiosource(4) = '1') then wave5 <= F;			else wave5 <= (others=>'0'); end if; -6			if (audiosource(5) = '1') then wave6 <= E;			else wave6 <= (others=>'0'); end if; -7			if (audiosource(6) = '1') then wave7 <= D;			else wave7 <= (others=>'0'); end if; -8			if (audiosource(7) = '1') then wave8 <= CMid; else wave8 <= (others=>'0'); end if; ---			CASE seconds IS				WHEN "000" => dout <= wave1; --A WHEN "001" => dout <= wave2; --B WHEN "010" => dout <= wave3; --C WHEN "011" => dout <= wave4; --D WHEN "100" => dout <= wave5; --E WHEN "101" => dout <= wave6; --F WHEN "110" => dout <= wave7; --G WHEN OTHERS => dout <= wave8; --A END CASE; end if; end process;

end Behavioral;


 * 1) UCF file for the Papilio One 500K & 250K boards
 * 2) Generated by pin_converter, written by Kevin Lindsey
 * 3) https://github.com/thelonious/papilio_pins/tree/development/pin_converter


 * 1) Main board wing pin [] to FPGA pin Pxx map
 * 2) ---C---    ---B---    ---A---
 * 3) [GND] [C00] P91    [GND] [B00] P85    P86 [A15]
 * 4) [2V5] [C01] P92    [2V5] [B01] P83    P84 [A14]
 * 5) [3V3] [C02] P94    [3V3] [B02] P78    P79 [A13]
 * 6) [5V0] [C03] P95    [5V0] [B03] P71    P70 [A12]
 * 7)       [C04] P98          [B04] P68    P67 [A11] [5V0]
 * 8)       [C05] P2           [B05] P66    P65 [A10] [3V3]
 * 9)       [C06] P3           [B06] P63    P62 [A09] [2V5]
 * 10)       [C07] P4           [B07] P61    P60 [A08] [GND]
 * 11) [GND] [C08] P5     [GND] [B08] P58    P57 [A07]
 * 12) [2V5] [C09] P9     [2V5] [B09] P54    P53 [A06]
 * 13) [3V3] [C10] P10    [3V3] [B10] P41    P40 [A05]
 * 14) [5V0] [C11] P11    [5V0] [B11] P36    P35 [A04]
 * 15)       [C12] P12          [B12] P34    P33 [A03] [5V0]
 * 16)       [C13] P15          [B13] P32    P26 [A02] [3V3]
 * 17)       [C14] P16          [B14] P25    P23 [A01] [2V5]
 * 18)       [C15] P17          [B15] P22    P18 [A00] [GND]


 * 1) Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
 * 2) CONFIG PROHIBIT=P99;
 * 3) CONFIG PROHIBIT=P43;
 * 4) CONFIG PROHIBIT=P42;
 * 5) CONFIG PROHIBIT=P39;
 * 6) CONFIG PROHIBIT=P49;
 * 7) CONFIG PROHIBIT=P48;
 * 8) CONFIG PROHIBIT=P47;
 * 9) CONFIG PART=XC3S250E-VQ100-4;
 * 10) CONFIG PART=XC3S500E-VQ100-4;

NET CLK         LOC="P89"  | IOSTANDARD=LVTTL | PERIOD=31.25ns;               # CLK NET AUDIO       LOC="P41"  | IOSTANDARD=LVTTL;                                # B10 NET SWITCH(0)   LOC="P4"  | IOSTANDARD=LVTTL;                                # C0 NET SWITCH(1)    LOC="P3"  | IOSTANDARD=LVTTL;                                # C1 NET SWITCH(2)    LOC="P2"  | IOSTANDARD=LVTTL;                                # C2 NET SWITCH(3)    LOC="P98"  | IOSTANDARD=LVTTL;                                # C3 NET SWITCH(4)    LOC="P95"  | IOSTANDARD=LVTTL;                                # C4 NET SWITCH(5)    LOC="P94"   | IOSTANDARD=LVTTL;                                # C5 NET SWITCH(6)    LOC="P92"   | IOSTANDARD=LVTTL;                                # C6 NET SWITCH(7)    LOC="P91"   | IOSTANDARD=LVTTL;                                # C7
 * 1) NET RX          LOC="P90"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # RX
 * 2) NET TX          LOC="P88"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX
 * 3) NET Seg7_AN(3)  LOC="P18"  | IOSTANDARD=LVTTL;                                # A0
 * 4) NET Seg7_DP     LOC="P23"  | IOSTANDARD=LVTTL;                                # A1
 * 5) NET Seg7_AN(2)  LOC="P26"  | IOSTANDARD=LVTTL;                                # A2
 * 6) NET Seg7_E      LOC="P33"  | IOSTANDARD=LVTTL;                                # A3
 * 7) NET Seg7_F      LOC="P35"  | IOSTANDARD=LVTTL;                                # A4
 * 8) NET Seg7_C      LOC="P40"  | IOSTANDARD=LVTTL;                                # A5
 * 9) NET Seg7_D      LOC="P53"  | IOSTANDARD=LVTTL;                                # A6
 * 10) NET Seg7_A      LOC="P57"  | IOSTANDARD=LVTTL;                                # A7
 * 11) NET Seg7_AN(1)  LOC="P60"  | IOSTANDARD=LVTTL;                                # A8
 * 12) NET Seg7_G      LOC="P62"  | IOSTANDARD=LVTTL;                                # A9
 * 13) NET Seg7_B      LOC="P65"  | IOSTANDARD=LVTTL;                                # A10
 * 14) NET Seg7_AN(0)  LOC="P67"  | IOSTANDARD=LVTTL;                                # A11
 * 15) BEGIN##################ALTERNATE NAMING FOR SEVEN SEGMENT PINS#####################
 * 16) NET "anodes<0>" 	LOC="P18"	| IOSTANDARD=LVTTL;											#####
 * 17) NET "anodes<1>" 	LOC="P26"	| IOSTANDARD=LVTTL;											#####
 * 18) NET "anodes<2>" 	LOC="P60"	| IOSTANDARD=LVTTL;											#####
 * 19) NET "anodes<3>" 	LOC="P67"	| IOSTANDARD=LVTTL;											#####
 * 20) NET "segments<6>" LOC="P62"	| IOSTANDARD=LVTTL;											#####
 * 21) NET "segments<5>" LOC="P35"	| IOSTANDARD=LVTTL;											#####
 * 22) NET "segments<4>" LOC="P33"	| IOSTANDARD=LVTTL;											#####
 * 23) NET "segments<3>" LOC="P53"	| IOSTANDARD=LVTTL;											#####
 * 24) NET "segments<2>" LOC="P40"	| IOSTANDARD=LVTTL;											#####
 * 25) NET "segments<1>" LOC="P65"	| IOSTANDARD=LVTTL;											#####
 * 26) NET "segments<0>" LOC="P57"	| IOSTANDARD=LVTTL;											#####
 * 27) NET "dp" 			LOC="P23"	| IOSTANDARD=LVTTL;											#####
 * 28) FINISH##################ALTERNATE NAMING FOR SEVEN SEGMENT PINS#####################
 * 29) NET SPI_CS      LOC="P70"  | IOSTANDARD=LVTTL;                                # A12
 * 30) NET SPI_MISO    LOC="P79"  | IOSTANDARD=LVTTL;                                # A13
 * 31) NET SPI_MOSI    LOC="P84"  | IOSTANDARD=LVTTL;                                # A14
 * 32) NET SPI_SCLK    LOC="P86"  | IOSTANDARD=LVTTL;                                # A15
 * 33) NET VGA_VSYNC   LOC="P85"  | IOSTANDARD=LVTTL;                                # B0
 * 34) NET VGA_HSYNC   LOC="P83"  | IOSTANDARD=LVTTL;                                # B1
 * 35) NET VGA_BLUE(0) LOC="P78"  | IOSTANDARD=LVTTL;                                # B2
 * 36) NET VGA_BLUE(1) LOC="P71"  | IOSTANDARD=LVTTL;                                # B3
 * 37) NET VGA_GREEN(0) LOC="P68" | IOSTANDARD=LVTTL;                                # B4
 * 38) NET VGA_GREEN(1) LOC="P66" | IOSTANDARD=LVTTL;                                # B5
 * 39) NET VGA_GREEN(2) LOC="P63" | IOSTANDARD=LVTTL;                                # B6
 * 40) NET VGA_RED(0)  LOC="P61"  | IOSTANDARD=LVTTL;                                # B7
 * 41) NET VGA_RED(1)  LOC="P58"  | IOSTANDARD=LVTTL;                                # B8
 * 42) NET VGA_RED(2)  LOC="P54"  | IOSTANDARD=LVTTL;                                # B9
 * 1) NET VGA_RED(2)  LOC="P54"  | IOSTANDARD=LVTTL;                                # B9
 * 1) NET JOY_RIGHT   LOC="P36"  | IOSTANDARD=LVTTL;                                # B11
 * 2) NET JOY_LEFT    LOC="P34"  | IOSTANDARD=LVTTL;                                # B12
 * 3) NET JOY_DOWN    LOC="P32"  | IOSTANDARD=LVTTL;                                # B13
 * 4) NET JOY_UP      LOC="P25"  | IOSTANDARD=LVTTL;                                # B14
 * 5) NET JOY_SELECT  LOC="P22"  | IOSTANDARD=LVTTL;                                # B15
 * 1) NET LED(0)      LOC="P17"   | IOSTANDARD=LVTTL;                                # C8
 * 2) NET LED(1)      LOC="P16"   | IOSTANDARD=LVTTL;                                # C9
 * 3) NET LED(2)      LOC="P15"  | IOSTANDARD=LVTTL;                                # C10
 * 4) NET LED(3)      LOC="P12"  | IOSTANDARD=LVTTL;                                # C11
 * 5) NET LED(4)      LOC="P11"  | IOSTANDARD=LVTTL;                                # C12
 * 6) NET LED(5)      LOC="P10"  | IOSTANDARD=LVTTL;                                # C13
 * 7) NET LED(6)      LOC="P9"  | IOSTANDARD=LVTTL;                                # C14
 * 8) NET LED(7)      LOC="P5"  | IOSTANDARD=LVTTL;                                # C15
 * 9) NET JTAG_TMS    LOC="P75"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TMS
 * 10) NET JTAG_TCK    LOC="P77"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TCK
 * 11) NET JTAG_TDI    LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TDI
 * 12) NET JTAG_TDO    LOC="P76"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TDO
 * 13) NET FLASH_CS    LOC="P24"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # FLASH_CS
 * 14) NET FLASH_CK    LOC="P50"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # FLASH_CK
 * 15) NET FLASH_SI    LOC="P27"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # FLASH_SI
 * 16) NET FLASH_SO    LOC="P44"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO

=Demo=

Click here for a video demonstration of the papilio simultaneously playing 8 sounds

Click here for the GitHub repository for this project

Click here for video and sound playing 8 notes.

=Next Steps=
 * Use keyboard of a computer as "piano keys" instead of the switches on the Papilio.
 * Play more than the 8-notes created already.
 * Figure out a way to tie this project with the Electronic Music Interface project
 * Replace the block memory audio samples with some type of audio input from an Arduino
 * Merge this multiplexer with the Papilio FM transmitter and create a demultiplexer/FM-receiver to create a sort of encrypted communications over the air.
 * Add digital filter to eliminate all the harmonics