User:1sfoerster/enes245/spring/arduinoToPapilio

Problem
The goal is to connect an Arduino Uno to a Papilio One and send data from the Arduino Uno to Papilio One.

Conceive
The entire project is inspired from Xilinx VHDL UART Example

Design


Arduino Uno Schematic

Papilio One Circuit Schematic

Papilio One Pinout

ASCII - Table

Below are all the codes

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity Arduino_to_Papilio is		Port(tx : out STD_LOGIC;			  SWITCH: in STD_LOGIC_VECTOR(7 downto 0);			  extclk : in STD_LOGIC			  );

end Arduino_to_Papilio;

architecture Behavioral of Arduino_to_Papilio is

component A2P port(data_in  : in std_logic_vector(7 downto 0);           write_buffer : in std_logic;           reset_buffer : in std_logic;           en_16_x_baud : in std_logic;           serial_out : out std_logic;           buffer_full : out std_logic;           buffer_half_full : out std_logic;           clk : in std_logic); end component;

COMPONENT dcm32to96 PORT(CLKIN_IN : IN std_logic;         			  CLKFX_OUT : OUT std_logic;		     CLKIN_IBUFG_OUT : OUT std_logic;		     CLK0_OUT : OUT std_logic		     );

END COMPONENT;

signal data_present, en_16_x_baud, clk, clk32 : STD_LOGIC; signal baud_count : integer range 0 to 5 :=0; signal clk_0			: std_logic;

begin

baud_timer: process(clk) begin if clk'event and clk='1' then if baud_count=1 then baud_count <= 0; en_16_x_baud <= '1'; else baud_count <= baud_count + 1; en_16_x_baud <= '0'; end if; end if; end process baud_timer;

Inst_dcm32to96: dcm32to96 PORT MAP(CLKIN_IN => extclk,					CLKFX_OUT => clk,					CLKIN_IBUFG_OUT => open,					CLK0_OUT => open					);

INST_A2P : A2P port map(data_in(6 downto 0) => SWITCH(6 downto 0),					data_in(7) => '0',					write_buffer => SWITCH(7),					reset_buffer => '0',					en_16_x_baud => en_16_x_baud,					clk => clk,					serial_out => tx,					buffer_half_full => open,					buffer_full => open					);

end Behavioral;

Here is the Module(A2P) of Main

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY UNISIM; USE UNISIM.VCOMPONENTS.ALL;

entity A2P is		Port(data_in : in std_logic_vector(7 downto 0);          write_buffer : in std_logic;           reset_buffer : in std_logic;           en_16_x_baud : in std_logic;           serial_out : out std_logic;           buffer_full : out std_logic;           buffer_half_full : out std_logic;           clk : in std_logic);

end A2P;

architecture macro_level_definition of A2P is

component kcuart_tx Port(data_in : in std_logic_vector(7 downto 0);          send_character : in std_logic;           en_16_x_baud : in std_logic;           serial_out : out std_logic;           Tx_complete : out std_logic;           clk : in std_logic); end component;

component bbfifo_16x8 Port(data_in : in std_logic_vector(7 downto 0);          data_out : out std_logic_vector(7 downto 0);           reset : in std_logic;                          write : in std_logic;            read : in std_logic;           full : out std_logic;           half_full : out std_logic;           data_present : out std_logic;           clk : in std_logic); end component;

signal fifo_data_out     : std_logic_vector(7 downto 0); signal fifo_data_present : std_logic; signal fifo_read         : std_logic;

begin

kcuart: kcuart_tx port map(data_in => fifo_data_out,					send_character => fifo_data_present,              en_16_x_baud => en_16_x_baud,               serial_out => serial_out,               Tx_complete => fifo_read,               clk => clk);

buf: bbfifo_16x8 port map(data_in => data_in,              data_out => fifo_data_out,               reset => reset_buffer,                             write => write_buffer,               read => fifo_read,               full => buffer_full,               half_full => buffer_half_full,               data_present => fifo_data_present,               clk => clk);

end macro_level_definition;

Here is the code of Sub-Modules of Module(A2P)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; --

-- -- Main Entity for KCUART_TX -- entity kcuart_tx is   Port (        data_in : in std_logic_vector(7 downto 0);           send_character : in std_logic;             en_16_x_baud : in std_logic;               serial_out : out std_logic;              Tx_complete : out std_logic;                      clk : in std_logic); end kcuart_tx; --

-- -- Start of Main Architecture for KCUART_TX --	 architecture low_level_definition of kcuart_tx is --

--

-- -- Signals used in KCUART_TX --

-- signal data_01           : std_logic; signal data_23           : std_logic; signal data_45           : std_logic; signal data_67           : std_logic; signal data_0123         : std_logic; signal data_4567         : std_logic; signal data_01234567     : std_logic; signal bit_select        : std_logic_vector(2 downto 0); signal next_count        : std_logic_vector(2 downto 0); signal mask_count        : std_logic_vector(2 downto 0); signal mask_count_carry  : std_logic_vector(2 downto 0); signal count_carry       : std_logic_vector(2 downto 0); signal ready_to_start    : std_logic; signal decode_Tx_start   : std_logic; signal Tx_start          : std_logic; signal decode_Tx_run     : std_logic; signal Tx_run            : std_logic; signal decode_hot_state  : std_logic; signal hot_state         : std_logic; signal hot_delay         : std_logic; signal Tx_bit            : std_logic; signal decode_Tx_stop    : std_logic; signal Tx_stop           : std_logic; signal decode_Tx_complete : std_logic; -- --

-- -- Attributes to define LUT contents during implementation -- The information is repeated in the generic map for functional simulation-- --

-- attribute INIT : string; attribute INIT of mux1_lut     : label is "E4FF"; attribute INIT of mux2_lut     : label is "E4FF"; attribute INIT of mux3_lut     : label is "E4FF"; attribute INIT of mux4_lut     : label is "E4FF"; attribute INIT of ready_lut    : label is "10"; attribute INIT of start_lut    : label is "0190"; attribute INIT of run_lut      : label is "1540"; attribute INIT of hot_state_lut : label is "94"; attribute INIT of delay14_srl  : label is "0000"; attribute INIT of stop_lut     : label is "0180"; attribute INIT of complete_lut : label is "8"; --

-- -- Start of KCUART_TX circuit description --

--	begin

-- 8 to 1 multiplexer to convert parallel data to serial

mux1_lut: LUT4 --synthesis translate_off generic map (INIT => X"E4FF") --synthesis translate_on port map( I0 => bit_select(0),           I1 => data_in(0),            I2 => data_in(1),            I3 => Tx_run,             O => data_01 );

mux2_lut: LUT4 --synthesis translate_off generic map (INIT => X"E4FF") --synthesis translate_on port map( I0 => bit_select(0),           I1 => data_in(2),            I2 => data_in(3),            I3 => Tx_run,             O => data_23 );

mux3_lut: LUT4 --synthesis translate_off generic map (INIT => X"E4FF") --synthesis translate_on port map( I0 => bit_select(0),           I1 => data_in(4),            I2 => data_in(5),            I3 => Tx_run,             O => data_45 );

mux4_lut: LUT4 --synthesis translate_off generic map (INIT => X"E4FF") --synthesis translate_on port map( I0 => bit_select(0),           I1 => data_in(6),            I2 => data_in(7),            I3 => Tx_run,             O => data_67 );

mux5_muxf5: MUXF5 port map( I1 => data_23,             I0 => data_01,              S => bit_select(1),              O => data_0123 );

mux6_muxf5: MUXF5 port map( I1 => data_67,             I0 => data_45,              S => bit_select(1),              O => data_4567 );

mux7_muxf6: MUXF6 port map( I1 => data_4567,             I0 => data_0123,              S => bit_select(2),              O => data_01234567 );

-- Register serial output and force start and stop bits

pipeline_serial: FDRS port map ( D => data_01234567,            Q => serial_out,             R => Tx_start,             S => Tx_stop,             C => clk);

-- 3-bit counter -- Counter is clock enabled by en_16_x_baud -- Counter will be reset when 'Tx_start' is active -- Counter will increment when Tx_bit is active -- Tx_run must be active to count -- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)

count_width_loop: for i in 0 to 2 generate -- attribute INIT : string; attribute INIT of count_lut : label is "8"; -- begin

register_bit: FDRE port map ( D => next_count(i),               Q => bit_select(i),               CE => en_16_x_baud,                R => Tx_start,                C => clk);

count_lut: LUT2 --synthesis translate_off generic map (INIT => X"8") --synthesis translate_on port map( I0 => bit_select(i),              I1 => Tx_run,                O => mask_count(i));

mask_and: MULT_AND port map( I0 => bit_select(i),              I1 => Tx_run,               LO => mask_count_carry(i));

lsb_count: if i=0 generate begin

count_muxcy: MUXCY port map( DI => mask_count_carry(i),                CI => Tx_bit,                  S => mask_count(i),                  O => count_carry(i)); count_xor: XORCY port map( LI => mask_count(i),                CI => Tx_bit,                  O => next_count(i));

end generate lsb_count;

upper_count: if i>0 generate begin

count_muxcy: MUXCY port map( DI => mask_count_carry(i),                CI => count_carry(i-1),                  S => mask_count(i),                  O => count_carry(i)); count_xor: XORCY port map( LI => mask_count(i),                CI => count_carry(i-1),                  O => next_count(i));

end generate upper_count;

end generate count_width_loop; -- Ready to start decode

ready_lut: LUT3 --synthesis translate_off generic map (INIT => X"10") --synthesis translate_on port map( I0 => Tx_run,           I1 => Tx_start,            I2 => send_character,             O => ready_to_start );

-- Start bit enable

start_lut: LUT4 --synthesis translate_off generic map (INIT => X"0190") --synthesis translate_on port map( I0 => Tx_bit,           I1 => Tx_stop,            I2 => ready_to_start,            I3 => Tx_start,             O => decode_Tx_start );

Tx_start_reg: FDE port map ( D => decode_Tx_start,            Q => Tx_start,            CE => en_16_x_baud,             C => clk);

-- Run bit enable

run_lut: LUT4 --synthesis translate_off generic map (INIT => X"1540") --synthesis translate_on port map( I0 => count_carry(2),           I1 => Tx_bit,            I2 => Tx_start,            I3 => Tx_run,             O => decode_Tx_run );

Tx_run_reg: FDE port map ( D => decode_Tx_run,            Q => Tx_run,            CE => en_16_x_baud,             C => clk);

-- Bit rate enable

hot_state_lut: LUT3 --synthesis translate_off generic map (INIT => X"94") --synthesis translate_on port map( I0 => Tx_stop,           I1 => ready_to_start,            I2 => Tx_bit,             O => decode_hot_state );

hot_state_reg: FDE port map ( D => decode_hot_state,            Q => hot_state,            CE => en_16_x_baud,             C => clk);

delay14_srl: SRL16E --synthesis translate_off generic map (INIT => X"0000") --synthesis translate_on port map(  D => hot_state,             CE => en_16_x_baud,            CLK => clk,             A0 => '1',             A1 => '0',             A2 => '1',             A3 => '1',              Q => hot_delay );

Tx_bit_reg: FDE port map ( D => hot_delay,            Q => Tx_bit,            CE => en_16_x_baud,             C => clk);

-- Stop bit enable

stop_lut: LUT4 --synthesis translate_off generic map (INIT => X"0180") --synthesis translate_on port map( I0 => Tx_bit,           I1 => Tx_run,            I2 => count_carry(2),            I3 => Tx_stop,             O => decode_Tx_stop );

Tx_stop_reg: FDE port map ( D => decode_Tx_stop,            Q => Tx_stop,            CE => en_16_x_baud,             C => clk);

-- Tx_complete strobe

complete_lut: LUT2 --synthesis translate_off generic map (INIT => X"8") --synthesis translate_on port map( I0 => count_carry(2),           I1 => en_16_x_baud,             O => decode_Tx_complete );

Tx_complete_reg: FD port map ( D => decode_Tx_complete,             Q => Tx_complete,             C => clk);

end low_level_definition;

-- -- END OF FILE KCUART_TX.VHD --

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; --

-- -- Main Entity for BBFIFO_16x8 -- entity bbfifo_16x8 is   Port (       data_in : in std_logic_vector(7 downto 0);                data_out : out std_logic_vector(7 downto 0);                   reset : in std_logic;                                  write : in std_logic;                     read : in std_logic;                    full : out std_logic;               half_full : out std_logic;            data_present : out std_logic;                     clk : in std_logic); end bbfifo_16x8; --

-- -- Start of Main Architecture for BBFIFO_16x8 --	 architecture low_level_definition of bbfifo_16x8 is --

--

-- -- Signals used in BBFIFO_16x8 --

-- signal pointer            : std_logic_vector(3 downto 0); signal next_count         : std_logic_vector(3 downto 0); signal half_count         : std_logic_vector(3 downto 0); signal count_carry        : std_logic_vector(2 downto 0);

signal pointer_zero       : std_logic; signal pointer_full       : std_logic; signal decode_data_present : std_logic; signal data_present_int   : std_logic; signal valid_write        : std_logic; -- --

-- -- Attributes to define LUT contents during implementation -- The information is repeated in the generic map for functional simulation-- --

-- attribute INIT : string; attribute INIT of zero_lut     : label is "0001"; attribute INIT of full_lut     : label is "8000"; attribute INIT of dp_lut       : label is "BFA0"; attribute INIT of valid_lut    : label is "C4"; --

-- -- Start of BBFIFO_16x8 circuit description --

--	begin

-- SRL16E data storage

data_width_loop: for i in 0 to 7 generate -- attribute INIT : string; attribute INIT of data_srl : label is "0000"; -- begin

data_srl: SRL16E --synthesis translate_off generic map (INIT => X"0000") --synthesis translate_on port map(  D => data_in(i),                CE => valid_write,               CLK => clk,                A0 => pointer(0),                A1 => pointer(1),                A2 => pointer(2),                A3 => pointer(3),                 Q => data_out(i) );

end generate data_width_loop; -- 4-bit counter to act as data pointer -- Counter is clock enabled by 'data_present' -- Counter will be reset when 'reset' is active -- Counter will increment when 'valid_write' is active

count_width_loop: for i in 0 to 3 generate -- attribute INIT : string; attribute INIT of count_lut : label is "6606"; -- begin

register_bit: FDRE port map ( D => next_count(i),               Q => pointer(i),               CE => data_present_int,                R => reset,                C => clk);

count_lut: LUT4 --synthesis translate_off generic map (INIT => X"6606") --synthesis translate_on port map( I0 => pointer(i),              I1 => read,               I2 => pointer_zero,               I3 => write,                O => half_count(i));

lsb_count: if i=0 generate begin

count_muxcy: MUXCY port map( DI => pointer(i),                CI => valid_write,                  S => half_count(i),                  O => count_carry(i)); count_xor: XORCY port map( LI => half_count(i),                CI => valid_write,                  O => next_count(i));

end generate lsb_count;

mid_count: if i>0 and i<3 generate begin

count_muxcy: MUXCY port map( DI => pointer(i),                CI => count_carry(i-1),                  S => half_count(i),                  O => count_carry(i)); count_xor: XORCY port map( LI => half_count(i),                CI => count_carry(i-1),                  O => next_count(i));

end generate mid_count;

upper_count: if i=3 generate begin

count_xor: XORCY port map( LI => half_count(i),                CI => count_carry(i-1),                  O => next_count(i));

end generate upper_count;

end generate count_width_loop;

-- Detect when pointer is zero and maximum

zero_lut: LUT4 --synthesis translate_off generic map (INIT => X"0001") --synthesis translate_on port map( I0 => pointer(0),           I1 => pointer(1),            I2 => pointer(2),            I3 => pointer(3),             O => pointer_zero );

full_lut: LUT4 --synthesis translate_off generic map (INIT => X"8000") --synthesis translate_on port map( I0 => pointer(0),           I1 => pointer(1),            I2 => pointer(2),            I3 => pointer(3),             O => pointer_full );

-- Data Present status

dp_lut: LUT4 --synthesis translate_off generic map (INIT => X"BFA0") --synthesis translate_on port map( I0 => write,           I1 => read,            I2 => pointer_zero,            I3 => data_present_int,             O => decode_data_present );

dp_flop: FDR port map ( D => decode_data_present,            Q => data_present_int,             R => reset,             C => clk);

-- Valid write signal

valid_lut: LUT3 --synthesis translate_off generic map (INIT => X"C4") --synthesis translate_on port map( I0 => pointer_full,           I1 => write,            I2 => read,             O => valid_write );

-- assign internal signals to outputs

full <= pointer_full; half_full <= pointer(3); data_present <= data_present_int;

end low_level_definition;

-- -- END OF FILE BBFIFO_16x8.VHD --

Here is the code for an Arduino

void setup { // initialize digital pins as an output. pinMode(13, OUTPUT); pinMode(12, OUTPUT); pinMode(11, OUTPUT); pinMode(10, OUTPUT); pinMode(9, OUTPUT); pinMode(8, OUTPUT); pinMode(7, OUTPUT); pinMode(6, OUTPUT); }

void loop { digitalWrite(13, HIGH); digitalWrite(12, HIGH); digitalWrite(11, HIGH); delay(random(300)); digitalWrite(11, LOW); delay(random(300)); digitalWrite(10, HIGH); delay(random(300)); digitalWrite(10, LOW); delay(random(300)); digitalWrite(9, HIGH); delay(random(300)); digitalWrite(9, LOW); delay(random(300)); digitalWrite(8, HIGH); delay(random(300)); digitalWrite(8, LOW); delay(random(300)); digitalWrite(7, HIGH); delay(random(300)); digitalWrite(7, LOW); delay(random(300));

digitalWrite(6, HIGH); delay(random(300)); digitalWrite(6, LOW); delay(random(300)); }

Implement
The data transmission from an Arduino to Papilio is done asynchronously, so there wont be any clock required. There are 8-output(wires) coming out of Arduino pins, first one acts as a switch to turn the transmission on or off, rest seven of them represent binary ASCII. All eight wires go straight from Arduino pins into the papilio's wingslot C pins. The data is then transmitted from Papilio into the computer. Putty screen will display the actual character that binary ASCII represents.

Next Steps
The only thing being transmitted are 1's and 0's, no null, framing, no sync, no error detection, no error correction. Need to start adding these thing.

From the null detect arduino clock and build this clock in the papilio.