User:ChangeMe

1. OR1200 CPU (www.opencores.com)]

The OpenRISC 1200 processor is a part of the following system:

The OR1200 CPU is a RISC CPU with a 5-stage pipeline. It was developed in the OpenRisk project. The whole hardver is open, we can use it freely the whole Verilog codes. It has Hardvard architechture, separated instruction and separated data memory management.

Block diagram of the OR1200 CPU

Cash
Harvard model with split instruction and data cache Instruction/data cache size scalable from 1KB to 64KB

I/O
It has no separate Input/Out Unit. It has Memory mapped I/O.

Registers
The processor support 32 general purpose 32-bit registers.

Pipeline
Scalar, single-issue 5-stage pipeline delivering sustained throughput.

Interrupts
It has 2 non-maskable, 30 maskable interrupt sources, and two interrupt priorities level. The Interrupts are used for the Task-Scheduling. It is called Programmable Interrupt Controller (PIC).

Instruction set
The instruction set is grouped into the Program Control Group, Logical Group, Arithemtic Group, Shift and Rotate Group, Input/Output Group and Interrupt Group. In total the processor supports 3 operands instructions. The most instructions execute in 1 clock cycles. The istruction set is the standard ORBIS32 type.