User:Sirnails

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I'm a professional FPGA engineer with a passion for electronic engineering and technology.

I'm a regular guy who welcomes any corrections if I'm veering off track. Back in 2009, I proudly earned my BEng in Electronic Engineering from Birmingham City University in the UK. Since 2013, my journey has revolved around the captivating realm of FPGA technology.

My skillset encompasses diverse areas, reflecting my curiosity and dedication. I've delved into programming PC Software, utilizing languages like Delphi, C, C++, and Java. Additionally, I've dived into embedded systems, using C and even a bit of assembler. My true forte, however, lies in FPGA development using VHDL, where I've cultivated considerable expertise.

Matlab/Simulink is another realm where I comfortably navigate, holding an above-intermediate proficiency. I've come to appreciate the role of Model-Based Design (MBD) in grappling with complex systems, particularly in the context of safety-critical marine vehicles. MBD offers an executable model that elegantly encapsulates system operations, easing the ordeal of handling complexity.

My most recent endeavor is the Model Descriptive Development Process (MDDP), a fusion of MBD and traditional text-based requirement methods. With this approach, I've meticulously dissected requirements, ensuring accurate FPGA implementation. Over a decade of experience with MathWorks tools in generating HDL for safety-critical systems has armed me with valuable insights.

I've harnessed simulink's power to craft intricate models that succinctly capture system behavior. By using Simulink to model and simulate the desired behavior of my FPGA design, I'm able to validate functionality and iron out issues before even delving into the VHDL implementation phase.

Once my Simulink model has been thoroughly tested and refined, I employ MathWorks tools to automatically convert it into synthesisable VHDL. This translation process ensures that the VHDL code mirrors the behavior described in the Simulink model. This seamless transition from model to code accelerates development while minimizing the chances of errors creeping in.

The synthesisable VHDL code generated from Simulink serves as the foundation for the FPGA design.

While I've only scratched the surface of control systems principles, I'm always eager to learn more. If you're interested in discussing these concepts, don't hesitate to drop me a line.

My professional journey has led me through diverse industries, including automotive, vision systems, defense, and power electronics. Navigating through these varied landscapes, I've gained insights into the intricacies and demands of each sector.

Thanks in advance,

Dave Sirnails (discuss • contribs) 13:11, 28 August 2023 (UTC)