VHDL/Introduction to VHDL

Lesson introduction
Welcome to the introductory lesson on VHDL (VHSIC Hardware Description Language). In this lesson, we'll provide you with a comprehensive overview of VHDL and its significance in the world of FPGA design. Unlike other technical lessons, this session aims to lay the foundation by highlighting the fundamental differences between VHDL and software programming. We'll delve into the context in which VHDL is utilised and explore less technical aspects associated with its role in FPGA design. By the end of this lesson, you'll not only appreciate what VHDL is but also gain insight into its applications within the design process.

Lesson Duration
For a focused reader with some technical background, 10-15 minutes for a close reading of the full text would be reasonable.

Lesson Objectives
After completing this lesson, learners will acquire the ability to:


 * 1) Differentiate between VHDL and software programming.
 * 2) Describe VHDL and explain its fundamental principles concisely to demonstrate comprehension.
 * 3) Describe the applications and contexts for VHDL's common usage.
 * 4) Describe VHDL's unique features for capturing hardware behaviors.
 * 5) Describe VHDL's role within the design process.
 * 6) Describe the historical evolution of VHDL, including its versions and development over time.
 * 7) Identify the stages of the VHDL design flow, encompassing design entry, simulation, synthesis, and hardware programming.
 * 8) Explain the need and uses of VHDL-related tools such as design capture, simulators, synthesis tools (netlist mapping, place and route, timing analysis), and hardware-related technologies like JTAG.

Preparation
No preparation on part of a learner is required for this lesson.

Lesson Resources
No special resources are needed for this lesson.

Overview of VHDL
VHDL, stands for Very High Speed Integrated Circuit Hardware Description Language is a language used to describe digital hardware systems. It is an international standard, regulated by the IEEE and is precisely and completely defined by the Language Reference Manual (LRM). VHDL can describe the behavior and structure of electronic systems, including ASICs, FPGAs, and conventional digital circuits. Engineers use VHDL code to express the desired behavior of a circuit, which is then transformed into a synthesized circuit netlist through a process called synthesis. The netlist is then placed and routed by a program that allocates physical resources within the architecture. VHDL allows designs to be described using any methodology and at any level of abstraction.

It is important to note that VHDL is not an information model, a database schema, a simulator, a toolset or a methodology, but rather a notation that is used in conjunction with these tools and methodologies. Simulation and synthesis are the two main kinds of tools that operate on VHDL.

Categorisation
VHDL falls under the imperative paradigm as it describes the behavior and structure of digital circuits, specifying “how” a circuit should function and “how” components are interconnected.

Low-Level vs. High-Level: VHDL is a low-level language in the context of hardware design. It provides precise control over the hardware’s behavior and structure, allowing engineers to define the logic gates and connections at a very detailed level.

Compiled vs. Interpreted: VHDL code is typically compiled into a netlist, which represents the digital circuit’s structure. This netlist can then be synthesized into hardware configurations.

VHDL is strongly typed: When a programming language is described as "strongly typed" it means that the language enforces strict rules regarding the data types of variables and how they can be used. In such languages, you can't perform operations that mix incompatible data types without explicit type conversion. This strong type checking helps prevent common programming errors and ensures that variables are used consistently according to their defined types.

VHDL uses static typing, where data types are explicitly defined for signals and variables, and these types remain fixed during simulation and synthesis.

VHDL is case insensitive, meaning that keywords can be written in upper or lower case. Identifiers (such as signal and variable names) are also not case sensitive.

VHDL is specifically designed for hardware description and simulation. Engineers use it to model and simulate digital circuits before synthesizing them into actual hardware.

VHDL is not tied to a specific platform but is widely supported by various EDA (Electronic Design Automation) tools and FPGA vendors, making it a cross-platform language for digital design.

Comparing VHDL and Software Programming
Even though a Hardware Description Language (HDL) might appear similar to regular programming languages, they possess significant distinctions.

A hardware description language is inherently parallel, this means that the commands, which represent logic gates, are carried out simultaneously when a new input is received.

HDL imitates how a physical system functions, often a digital one and can detail timing details (such as gate propegation delays) and the description of a system as a connection of components.


 * VHDL modeling requires knowledge of digital logic, hardware building blocks and how they interconnect. Software programming requires knowledge of data structures, algorithms, controlling program flow and programming techniques.
 * VHDL is a hardware description language used to design and model digital circuits and systems, while software programming languages like C, Python, etc. are used to create software programs that run on processors.
 * In VHDL, concurrency and parallelism are inherent as hardware circuits run concurrently. Software programs are generally sequential and require threads/processes for concurrency.
 * VHDL has built-in facilities for modeling timing and delays which are critical for hardware. Software programming languages don't have inherent support for timing or delays.
 * VHDL code is executed by synthesis tools to generate digital circuits. Software code is compiled into machine code and executed sequentially by a processor.

Here are some key differences between VHDL and software programming languages:
 * Concurrency - VHDL inherently supports modeling concurrent and parallel hardware processes versus sequential software.
 * Timing - VHDL has built-in timing and delay modeling constructs to define hardware speed and performance.
 * Synthesis - VHDL models can be directly synthesized into digital hardware, software requires compilation for a processor.
 * Abstraction - VHDL models focus on architectural function rather than low-level software algorithms.
 * Verification - VHDL enables rigorous system verification through testbenches and assertions.
 * Standardization - VHDL is an IEEE standard language with strong industry adoption.
 * Documentation - VHDL provides explicit documentation of the hardware functionality.
 * Portability - VHDL models can be reused and migrated between target devices.
 * Determinism - The output of VHDL hardware is deterministic compared to software stacks.
 * Reliability - FPGAs have fixed hardware resources so performance is predictable compared to variable software loads.
 * Reusability - VHDL code can be ported to new target devices enabling reuse as old devices become obsolete.

Historical Context
VHDL originated in the early 1980s as part of a U.S Department of Defense program to standardize integrated circuit design and documentation of the components that supplier companies were including in equipment. In 1987, it was standardized by the IEEE as IEEE 1076, which helped drive broader industry adoption beyond just defense contractors. By the late 80s and into the 90s, commercial EDA tools started incorporating VHDL, enabling practical use for simulation, synthesis, and other parts of the IC design flow.

Several versions of VHDL have been released over the years, including those in 1987, 1993, 2002, 2008 and 2019.

During the application-specific integrated circuit (ASIC) revolution in the 1990s, VHDL became widely used for designing complex ASIC chips across sectors like telecommunications, networking, and consumer electronics. Later, with the rise of field-programmable gate array (FPGA) devices, VHDL and its competitor Verilog became essential languages for programming FPGAs from companies like Xilinx and Altera. This drove massive growth in the use of HDLs like VHDL.

VHDL's ability to thoroughly verify functionality through testbenches and simulations has made it very popular for functional verification. Along with Verilog, VHDL is now supported across all major EDA vendors and embedded in tool flows as a standard modeling language. VHDL has enabled extensive design re-use through the creation of standardized IP cores and design blocks. It provides rigorous documentation of hardware behavior, aiding IP protection and technical hand-offs. Thanks to these factors - strong tool support, verification, re-usability, and standardization - VHDL has become ubiquitous across the digital IC design industry.

VHDL is the most commonly used and arguably the most powerful hardware descriptive language in use, with the runners up being Verilog and AHDL.

Importance in Digital Design
VHDL plays a very important role in modern digital design by providing a standardized language for describing and specifying hardware behavior and structure.

At its core, VHDL enables precise and unambiguous specification of a digital system's functionality and architecture. This acts as the golden reference for implementation. VHDL goes beyond just behavior - it can also capture structural aspects like hierarchies, interfaces and connectivity. Timing constraints and delays can also be modeled to define temporal relationships. This level of specification is critical for complex digital systems.

Compared to older HDLs like AHDL or ABEL, VHDL provides much richer capabilities to model concurrency, dataflow behavior, state machines, and other hardware paradigms. The strong typing and modularity in VHDL enables reusability and scalability. VHDL offers portability across vendors and a path to industry standardization which earlier HDLs lacked.

VHDL complements Verilog, another popular HDL standard. While Verilog originated from a modeling paradigm, VHDL was designed from requirements of documentation and simulation. This makes VHDL better suited for systems requiring rigorous specification to aid documentation. VHDL also excels at functional verification through extensive testbench support.

Key Concepts
VHDL designs are separated into entities, which encapsulate the external interfaces, and architectures, which define the internal implementation details. This separation enables re-use of the same entity with different architectures. Within architectures, concurrent processes model hardware parallelism and run in parallel like hardware gates and circuits. Sequential processes run sequentially like software procedures. Communication between concurrent processes is done using signals, which also represent hardware connections. Assignments to signals model the transfer of data and can incorporate timings/delays to capture hardware timing.

VHDL has a robust typing system with standard data types like bit, std_logic, integer as well as user-defined types like enums and records which enable creation of custom composite types. Resolved types represent hardware vector structures. The strong typing enables error checking and robust design. Other features like packages and libraries promote re-usability and productivity. With its emphasis on modeling structure, behavior and function over transistor-level implementations, VHDL enables productive top-down digital hardware design.

VHDL in the Design Flow
VHDL plays a central role in the overall digital design process. It enables designers to describe the required hardware behavior and structure at a high level of abstraction using a standardized language. This VHDL code serves as the master source from which the end hardware is ultimately derived through a series of tools.

The VHDL code is extensively simulated using testbenches to verify functionality before synthesis. VHDL's comprehensive simulation capabilities enable thorough validation at the design stage itself, ensuring bugs never make it into final hardware.

The verified VHDL code is then synthesized into lower level building blocks like logic gates by a synthesis tool. The synthesis tool essentially interprets the VHDL and generates an optimized gate level netlist while preserving the design's behavior and timing.

The synthesized netlist is then passed to placement and routing tools which transform the abstract gates and connections into a physical layout optimized for the target technology like an FPGA or ASIC. This layout maps the design to actual hardware resources.

For FPGAs, the VHDL code can be directly compiled into the programming binary file to configure the FPGA after synthesis and place-and-route. For ASICs, the final layout and geometries generated from VHDL are sent to a semiconductor foundry for fabrication.

This demonstrates VHDL's integral role in digital design - it sits at the front of an automated workflow from high level behavior to final physical implementation while enabling extensive verification via simulation. The use of VHDL drives the productivity and success of FPGA and ASIC implementations.

Industry Applications
VHDL is widely used across a range of real-world applications to efficiently design complex digital systems and integrated circuits. In high-performance computing, VHDL models the interconnect and memory architecture for massively parallel processors with thousands of cores. Telecommunication applications leverage VHDL to design the digital signal processing blocks in ASICs and FPGAs for 5G, LTE, packet processing. Automotive uses VHDL for engine control units, infotainment systems, ADAS chipsets which require extensive modeling of parallel hardware and interfaces.

Consumer electronics rely on VHDL's simulation capabilities to verify multimedia codec SoCs and graphics processors before taping out million-unit chips. Aerospace and defense applications use VHDL due to its origin as a military standard, taking advantage of rigorous documentation and precise specification enabled. The testbench and verification features allow thorough validation of mission-critical electronics.

Across these verticals, VHDL enables concise representation of system connectivity, timing, and functionality at a high level of abstraction. This drives faster design iteration and verification through simulation before synthesis. The standardized, portable nature of VHDL allows IP reuse across projects and migration to new foundry nodes and process technologies while retaining the same functionality. VHDL modeling enables accurate yet efficient design capture, allowing engineers to focus on architecture and interfaces rather than low-level implementation details. Its combination of productivity, verification, and consistency has cemented VHDL's status as an essential design language across electronics industries.

Presentation: [Presentation Title] (Estimated Time: [Time])

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Lab Work: [Lab Title] (Estimated Time: [Time])

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Additional Resources and Readings
https://en.wikipedia.org/wiki/VHDL

https://vhdlwhiz.com/what-is-vhdl/

https://www.doulos.com/knowhow/vhdl/what-is-vhdl/


 * Optionally provide supplementary resources for further exploration.
 * List recommended readings, online tutorials, or research papers.

Assessment
- Describe how student understanding and performance will be assessed for this lesson.

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Conclusion
- Summarise the key takeaways from the lesson.

- Highlight the connections between this lesson and the broader course objectives.

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