Verilog

Welcome to the Wikiversity content-development project for the Verilog language.

Introduction
Verilog is a Hardware description Language (HDL) originally began as a proprietary HDL of Cadence Design Systems. But Cadence transferred control of Verilog to a consortium of companies and universities known as Open Verilog International (OVI) as a step leading to its adoption as an IEEE standard.

Introductory Lessons

 * Introduction to Verilog
 * Basic Example


 * Basic Constructs
 * Primitives
 * Signals
 * Operators
 * Constants


 * Procedural Blocks
 * Initial Block
 * Always Block
 * Assignments
 * Hierarchy
 * System Tasks
 * Testbenches in Verilog