Verilog programming in plain view

Design Levels of Abstraction

 * Modeling Overview ([[Media:Vlog.Level.1.A.Overview.201305017.pdf |pdf]])
 * Gate-Level Modeling ([[Media:Vlog.Level.1.B.Gate.pdf |pdf]])
 * Dataflow Modeling ([[Media:Vlog.Level.1.C.Dataflow.pdf |pdf]])
 * Behavioral Modeling ([[Media:Vlog.Level.1.D.Behavioral.pdf |pdf]])

Simulation Timing
go to [ Electrical_%26_Computer_Engineering_Studies ]
 * Timing Model ([[Media:Vlog.Timing.1.A.Model.20130514.pdf |pdf]])
 * Assignments and Delays ([[Media:Vlog.Timing.1.A.DAssign.20131105.pdf |pdf]])
 * Blocking & NonBlocking Assignments
 * Assignments With Delays